f50k.map.qmsg

VHDL产生时钟50分频程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 02 16:30:21 2008 " "Info: Processing started: Sat Aug 02 16:30:21 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off f50k -c f50k " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off f50k -c f50k" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f50k.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file f50k.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 f50k-behav " "Info: Found design unit 1: f50k-behav" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 f50k " "Info: Found entity 1: f50k" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "f50k " "Info: Elaborating entity \"f50k\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset f50k.vhd(67) " "Warning (10492): VHDL Process Statement warning at f50k.vhd(67): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 67 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "c3 f50k.vhd(71) " "Warning (10492): VHDL Process Statement warning at f50k.vhd(71): signal \"c3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 71 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "qout f50k.vhd(117) " "Warning (10631): VHDL Process Statement warning at f50k.vhd(117): inferring latch(es) for signal or variable \"qout\", which holds its previous value in one or more paths through the process" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "qout\[0\] f50k.vhd(117) " "Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for \"qout\[0\]\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "qout\[1\] f50k.vhd(117) " "Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for \"qout\[1\]\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "qout\[2\] f50k.vhd(117) " "Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for \"qout\[2\]\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "qout\[3\] f50k.vhd(117) " "Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for \"qout\[3\]\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "qout\[4\] f50k.vhd(117) " "Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for \"qout\[4\]\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "qout\[5\] f50k.vhd(117) " "Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for \"qout\[5\]\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "qout\[6\] f50k.vhd(117) " "Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for \"qout\[6\]\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "qout\[7\] f50k.vhd(117) " "Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for \"qout\[7\]\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add3 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add3\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 141 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|addcore:adder lpm_add_sub:Add3 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add3\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 141 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add3 " "Info: Instantiated megafunction \"lpm_add_sub:Add3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 10 " "Info: Parameter \"LPM_WIDTH\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 141 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add3 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 141 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add3 " "Info: Instantiated megafunction \"lpm_add_sub:Add3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 10 " "Info: Parameter \"LPM_WIDTH\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 141 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}