f50k.map.rpt

VHDL产生时钟50分频程序

; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY               ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE               ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE             ;
+------------------------+-------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Aug 02 16:30:21 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off f50k -c f50k
Info: Found 2 design units, including 1 entities, in source file f50k.vhd
    Info: Found design unit 1: f50k-behav
    Info: Found entity 1: f50k
Info: Elaborating entity "f50k" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at f50k.vhd(67): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at f50k.vhd(71): signal "c3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at f50k.vhd(117): inferring latch(es) for signal or variable "qout", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for "qout[0]"
Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for "qout[1]"
Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for "qout[2]"
Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for "qout[3]"
Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for "qout[4]"
Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for "qout[5]"
Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for "qout[6]"
Info (10041): Verilog HDL or VHDL info at f50k.vhd(117): inferred latch for "qout[7]"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "lpm_add_sub:Add3"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Elaborated megafunction instantiation "lpm_add_sub:Add3|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:Add3"
Info: Instantiated megafunction "lpm_add_sub:Add3" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "10"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Elaborated megafunction instantiation "lpm_add_sub:Add3|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add3"
Info: Instantiated megafunction "lpm_add_sub:Add3" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "10"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add3"
Info: Instantiated megafunction "lpm_add_sub:Add3" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "10"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Elaborated megafunction instantiation "lpm_add_sub:Add3|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add3"
Info: Instantiated megafunction "lpm_add_sub:Add3" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "10"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add3|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add3"
Info: Instantiated megafunction "lpm_add_sub:Add3" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "10"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add2"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add2|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:Add2"
Info: Instantiated megafunction "lpm_add_sub:Add2" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "6"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add2|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add2"
Info: Instantiated megafunction "lpm_add_sub:Add2" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "6"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add2|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add2"
Info: Instantiated megafunction "lpm_add_sub:Add2" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "6"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add2|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add2"
Info: Instantiated megafunction "lpm_add_sub:Add2" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "6"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add1"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add1|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:Add1"
Info: Instantiated megafunction "lpm_add_sub:Add1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add1|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add1"
Info: Instantiated megafunction "lpm_add_sub:Add1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add1"
Info: Instantiated megafunction "lpm_add_sub:Add1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add1|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add1"
Info: Instantiated megafunction "lpm_add_sub:Add1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "14"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "14"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "14"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "14"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Warning: Latch qout[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal reset
Warning: Latch qout[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal reset
Warning: Latch qout[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal reset
Warning: Latch qout[3]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal reset
Warning: Latch qout[4]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal reset
Warning: Latch qout[5]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal reset
Warning: Latch qout[6]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal reset
Warning: Latch qout[7]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal reset
Info: Registers with preset signals will power-up high
Info: Implemented 264 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 8 output pins
    Info: Implemented 254 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings
    Info: Processing ended: Sat Aug 02 16:30:30 2008
    Info: Elapsed time: 00:00:10