f50k.fit.summary

来自「VHDL产生时钟50分频程序」· SUMMARY 代码 · 共 12 行

Fitter Status : Successful - Sat Aug 02 16:31:00 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : f50k
Top-level Entity Name : f50k
Family : ACEX1K
Device : EP1K100QC208-3
Timing Models : Final
Total logic elements : 254 / 4,992 ( 5 % )
Total pins : 10 / 147 ( 7 % )
Total memory bits : 0 / 49,152 ( 0 % )
Total PLLs : 0