subcont.v

Verilog 经典实例

module subcont
(
	clk,
	rst,
	cont
);
	input clk;
	input rst;
	output [7:0] cont;
	
	reg [7:0] cont;
	
	always @ (posedge clk, posedge rst)
	begin
		if (rst) cont <= 0;
		else cont <= cont - 1;
	end
endmodule