verilog_seg7.map.qmsg

Verilog 经典实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 19 23:21:17 2006 " "Info: Processing started: Sun Nov 19 23:21:17 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off verilog_seg7 -c verilog_seg7 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off verilog_seg7 -c verilog_seg7" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IACF_OBSOLETED_ASSIGNMENT_REMOVED" "TCL_SCRIPT_FILE " "Info: Assignment \"TCL_SCRIPT_FILE\" is no longer supported -- removing assignment from Quartus II Settings File" {  } {  } 0 0 "Assignment \"%1!s!\" is no longer supported -- removing assignment from Quartus II Settings File" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_seg7.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file verilog_seg7.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 verilog_seg7 " "Info: Found entity 1: verilog_seg7" {  } { { "verilog_seg7.bdf" "" { Schematic "D:/verilog_seg7/verilog_seg7.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "verilog_seg7 " "Info: Elaborating entity \"verilog_seg7\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "segmain.v 1 1 " "Warning: Using design file segmain.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 segmain " "Info: Found entity 1: segmain" {  } { { "segmain.v" "" { Text "D:/verilog_seg7/segmain.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segmain segmain:inst1 " "Info: Elaborating entity \"segmain\" for hierarchy \"segmain:inst1\"" {  } { { "verilog_seg7.bdf" "inst1" { Schematic "D:/verilog_seg7/verilog_seg7.bdf" { { 240 320 496 336 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 segmain.v(29) " "Warning (10230): Verilog HDL assignment warning at segmain.v(29): truncated value with size 32 to match size of target (2)" {  } { { "segmain.v" "" { Text "D:/verilog_seg7/segmain.v" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "datain segmain.v(44) " "Warning (10235): Verilog HDL Always Construct warning at segmain.v(44): variable \"datain\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "segmain.v" "" { Text "D:/verilog_seg7/segmain.v" 44 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "datain segmain.v(45) " "Warning (10235): Verilog HDL Always Construct warning at segmain.v(45): variable \"datain\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "segmain.v" "" { Text "D:/verilog_seg7/segmain.v" 45 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "datain segmain.v(46) " "Warning (10235): Verilog HDL Always Construct warning at segmain.v(46): variable \"datain\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "segmain.v" "" { Text "D:/verilog_seg7/segmain.v" 46 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "datain segmain.v(47) " "Warning (10235): Verilog HDL Always Construct warning at segmain.v(47): variable \"datain\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "segmain.v" "" { Text "D:/verilog_seg7/segmain.v" 47 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_counter0.vhd 2 1 " "Warning: Using design file lpm_counter0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_counter0-SYN " "Info: Found design unit 1: lpm_counter0-SYN" {  } { { "lpm_counter0.vhd" "" { Text "D:/verilog_seg7/lpm_counter0.vhd" 48 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Info: Found entity 1: lpm_counter0" {  } { { "lpm_counter0.vhd" "" { Text "D:/verilog_seg7/lpm_counter0.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 lpm_counter0:inst4 " "Info: Elaborating entity \"lpm_counter0\" for hierarchy \"lpm_counter0:inst4\"" {  } { { "verilog_seg7.bdf" "inst4" { Schematic "D:/verilog_seg7/verilog_seg7.bdf" { { 24 464 608 88 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../altera/quartus51/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../altera/quartus51/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter0:inst4\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.vhd" "lpm_counter_component" { Text "D:/verilog_seg7/lpm_counter0.vhd" 70 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_mad.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_mad.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_mad " "Info: Found entity 1: cntr_mad" {  } { { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_mad lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated " "Info: Elaborating entity \"cntr_mad\" for hierarchy \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "subcont.v 1 1 " "Warning: Using design file subcont.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 subcont " "Info: Found entity 1: subcont" {  } { { "subcont.v" "" { Text "D:/verilog_seg7/subcont.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "subcont subcont:inst5 " "Info: Elaborating entity \"subcont\" for hierarchy \"subcont:inst5\"" {  } { { "verilog_seg7.bdf" "inst5" { Schematic "D:/verilog_seg7/verilog_seg7.bdf" { { 112 360 472 208 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 subcont.v(16) " "Warning (10230): Verilog HDL assignment warning at subcont.v(16): truncated value with size 32 to match size of target (8)" {  } { { "subcont.v" "" { Text "D:/verilog_seg7/subcont.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "addcont.v 1 1 " "Warning: Using design file addcont.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 addcont " "Info: Found entity 1: addcont" {  } { { "addcont.v" "" { Text "D:/verilog_seg7/addcont.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcont addcont:inst " "Info: Elaborating entity \"addcont\" for hierarchy \"addcont:inst\"" {  } { { "verilog_seg7.bdf" "inst" { Schematic "D:/verilog_seg7/verilog_seg7.bdf" { { 112 592 704 208 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 addcont.v(16) " "Warning (10230): Verilog HDL assignment warning at addcont.v(16): truncated value with size 32 to match size of target (8)" {  } { { "addcont.v" "" { Text "D:/verilog_seg7/addcont.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "bin27seg.v 1 1 " "Warning: Using design file bin27seg.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 bin27seg " "Info: Found entity 1: bin27seg" {  } { { "bin27seg.v" "" { Text "D:/verilog_seg7/bin27seg.v" 14 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin27seg bin27seg:inst6 " "Info: Elaborating entity \"bin27seg\" for hierarchy \"bin27seg:inst6\"" {  } { { "verilog_seg7.bdf" "inst6" { Schematic "D:/verilog_seg7/verilog_seg7.bdf" { { 240 528 712 336 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "75 " "Info: Implemented 75 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "62 " "Info: Implemented 62 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 19 23:21:26 2006 " "Info: Processing ended: Sun Nov 19 23:21:26 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}