verilog_seg7.hier_info

Verilog 经典实例

|verilog_seg7
ledcom[0] <= segmain:inst1.ledcom[0]
ledcom[1] <= segmain:inst1.ledcom[1]
ledcom[2] <= segmain:inst1.ledcom[2]
ledcom[3] <= segmain:inst1.ledcom[3]
clk => lpm_counter0:inst4.clock
reset => inst7.IN0
seg7[0] <= bin27seg:inst6.data_out[0]
seg7[1] <= bin27seg:inst6.data_out[1]
seg7[2] <= bin27seg:inst6.data_out[2]
seg7[3] <= bin27seg:inst6.data_out[3]
seg7[4] <= bin27seg:inst6.data_out[4]
seg7[5] <= bin27seg:inst6.data_out[5]
seg7[6] <= bin27seg:inst6.data_out[6]


|verilog_seg7|segmain:inst1
clk => comclk[0].CLK
clk => comclk[1].CLK
rst => comclk[0].ACLR
rst => comclk[1].ACLR
datain[0] => bcd_led~11.DATAB
datain[1] => bcd_led~10.DATAB
datain[2] => bcd_led~9.DATAB
datain[3] => bcd_led~8.DATAB
datain[4] => bcd_led~7.DATAB
datain[5] => bcd_led~6.DATAB
datain[6] => bcd_led~5.DATAB
datain[7] => bcd_led~4.DATAB
datain[8] => bcd_led~3.DATAB
datain[9] => bcd_led~2.DATAB
datain[10] => bcd_led~1.DATAB
datain[11] => bcd_led~0.DATAB
datain[12] => bcd_led~3.DATAA
datain[13] => bcd_led~2.DATAA
datain[14] => bcd_led~1.DATAA
datain[15] => bcd_led~0.DATAA
dataout[0] <= bcd_led~11.DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= bcd_led~10.DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= bcd_led~9.DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= bcd_led~8.DB_MAX_OUTPUT_PORT_TYPE
ledcom[0] <= Equal~0.DB_MAX_OUTPUT_PORT_TYPE
ledcom[1] <= ledcom~4.DB_MAX_OUTPUT_PORT_TYPE
ledcom[2] <= ledcom~3.DB_MAX_OUTPUT_PORT_TYPE
ledcom[3] <= ledcom~2.DB_MAX_OUTPUT_PORT_TYPE


|verilog_seg7|lpm_counter0:inst4
clock => lpm_counter:lpm_counter_component.clock
q[0] <= lpm_counter:lpm_counter_component.q[0]
q[1] <= lpm_counter:lpm_counter_component.q[1]
q[2] <= lpm_counter:lpm_counter_component.q[2]
q[3] <= lpm_counter:lpm_counter_component.q[3]
q[4] <= lpm_counter:lpm_counter_component.q[4]
q[5] <= lpm_counter:lpm_counter_component.q[5]
q[6] <= lpm_counter:lpm_counter_component.q[6]
q[7] <= lpm_counter:lpm_counter_component.q[7]
q[8] <= lpm_counter:lpm_counter_component.q[8]
q[9] <= lpm_counter:lpm_counter_component.q[9]
q[10] <= lpm_counter:lpm_counter_component.q[10]
q[11] <= lpm_counter:lpm_counter_component.q[11]
q[12] <= lpm_counter:lpm_counter_component.q[12]
q[13] <= lpm_counter:lpm_counter_component.q[13]
q[14] <= lpm_counter:lpm_counter_component.q[14]
q[15] <= lpm_counter:lpm_counter_component.q[15]
q[16] <= lpm_counter:lpm_counter_component.q[16]
q[17] <= lpm_counter:lpm_counter_component.q[17]
q[18] <= lpm_counter:lpm_counter_component.q[18]
q[19] <= lpm_counter:lpm_counter_component.q[19]
q[20] <= lpm_counter:lpm_counter_component.q[20]
q[21] <= lpm_counter:lpm_counter_component.q[21]
q[22] <= lpm_counter:lpm_counter_component.q[22]
q[23] <= lpm_counter:lpm_counter_component.q[23]
q[24] <= lpm_counter:lpm_counter_component.q[24]
q[25] <= lpm_counter:lpm_counter_component.q[25]


|verilog_seg7|lpm_counter0:inst4|lpm_counter:lpm_counter_component
clock => cntr_mad:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
data[12] => ~NO_FANOUT~
data[13] => ~NO_FANOUT~
data[14] => ~NO_FANOUT~
data[15] => ~NO_FANOUT~
data[16] => ~NO_FANOUT~
data[17] => ~NO_FANOUT~
data[18] => ~NO_FANOUT~
data[19] => ~NO_FANOUT~
data[20] => ~NO_FANOUT~
data[21] => ~NO_FANOUT~
data[22] => ~NO_FANOUT~
data[23] => ~NO_FANOUT~
data[24] => ~NO_FANOUT~
data[25] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_mad:auto_generated.q[0]
q[1] <= cntr_mad:auto_generated.q[1]
q[2] <= cntr_mad:auto_generated.q[2]
q[3] <= cntr_mad:auto_generated.q[3]
q[4] <= cntr_mad:auto_generated.q[4]
q[5] <= cntr_mad:auto_generated.q[5]
q[6] <= cntr_mad:auto_generated.q[6]
q[7] <= cntr_mad:auto_generated.q[7]
q[8] <= cntr_mad:auto_generated.q[8]
q[9] <= cntr_mad:auto_generated.q[9]
q[10] <= cntr_mad:auto_generated.q[10]
q[11] <= cntr_mad:auto_generated.q[11]
q[12] <= cntr_mad:auto_generated.q[12]
q[13] <= cntr_mad:auto_generated.q[13]
q[14] <= cntr_mad:auto_generated.q[14]
q[15] <= cntr_mad:auto_generated.q[15]
q[16] <= cntr_mad:auto_generated.q[16]
q[17] <= cntr_mad:auto_generated.q[17]
q[18] <= cntr_mad:auto_generated.q[18]
q[19] <= cntr_mad:auto_generated.q[19]
q[20] <= cntr_mad:auto_generated.q[20]
q[21] <= cntr_mad:auto_generated.q[21]
q[22] <= cntr_mad:auto_generated.q[22]
q[23] <= cntr_mad:auto_generated.q[23]
q[24] <= cntr_mad:auto_generated.q[24]
q[25] <= cntr_mad:auto_generated.q[25]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|verilog_seg7|lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
clock => counter_cella12.CLK
clock => counter_cella13.CLK
clock => counter_cella14.CLK
clock => counter_cella15.CLK
clock => counter_cella16.CLK
clock => counter_cella17.CLK
clock => counter_cella18.CLK
clock => counter_cella19.CLK
clock => counter_cella20.CLK
clock => counter_cella21.CLK
clock => counter_cella22.CLK
clock => counter_cella23.CLK
clock => counter_cella24.CLK
clock => counter_cella25.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT
q[12] <= counter_cella12.REGOUT
q[13] <= counter_cella13.REGOUT
q[14] <= counter_cella14.REGOUT
q[15] <= counter_cella15.REGOUT
q[16] <= counter_cella16.REGOUT
q[17] <= counter_cella17.REGOUT
q[18] <= counter_cella18.REGOUT
q[19] <= counter_cella19.REGOUT
q[20] <= counter_cella20.REGOUT
q[21] <= counter_cella21.REGOUT
q[22] <= counter_cella22.REGOUT
q[23] <= counter_cella23.REGOUT
q[24] <= counter_cella24.REGOUT
q[25] <= counter_cella25.REGOUT


|verilog_seg7|subcont:inst5
clk => cont[6]~reg0.CLK
clk => cont[5]~reg0.CLK
clk => cont[4]~reg0.CLK
clk => cont[3]~reg0.CLK
clk => cont[2]~reg0.CLK
clk => cont[1]~reg0.CLK
clk => cont[0]~reg0.CLK
clk => cont[7]~reg0.CLK
rst => cont[6]~reg0.ACLR
rst => cont[5]~reg0.ACLR
rst => cont[4]~reg0.ACLR
rst => cont[3]~reg0.ACLR
rst => cont[2]~reg0.ACLR
rst => cont[1]~reg0.ACLR
rst => cont[0]~reg0.ACLR
rst => cont[7]~reg0.ACLR
cont[0] <= cont[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[1] <= cont[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[2] <= cont[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[3] <= cont[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[4] <= cont[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[5] <= cont[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[6] <= cont[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[7] <= cont[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|verilog_seg7|addcont:inst
clk => cont[6]~reg0.CLK
clk => cont[5]~reg0.CLK
clk => cont[4]~reg0.CLK
clk => cont[3]~reg0.CLK
clk => cont[2]~reg0.CLK
clk => cont[1]~reg0.CLK
clk => cont[0]~reg0.CLK
clk => cont[7]~reg0.CLK
rst => cont[6]~reg0.ACLR
rst => cont[5]~reg0.ACLR
rst => cont[4]~reg0.ACLR
rst => cont[3]~reg0.ACLR
rst => cont[2]~reg0.ACLR
rst => cont[1]~reg0.ACLR
rst => cont[0]~reg0.ACLR
rst => cont[7]~reg0.ACLR
cont[0] <= cont[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[1] <= cont[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[2] <= cont[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[3] <= cont[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[4] <= cont[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[5] <= cont[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[6] <= cont[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cont[7] <= cont[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|verilog_seg7|bin27seg:inst6
data_in[0] => Decoder~0.IN3
data_in[1] => Decoder~0.IN2
data_in[2] => Decoder~0.IN1
data_in[3] => Decoder~0.IN0
data_out[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE