verilog_seg7.hif

Verilog 经典实例

Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
34
1786
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
verilog_seg7
# storage
db|verilog_seg7.(0).cnf
db|verilog_seg7.(0).cnf
# case_insensitive
# source_file
verilog_seg7.bdf
8e3ced62c979397fdf342f1f2341e4a
23
# hierarchies {
|
}
# end
# entity
segmain
# storage
db|verilog_seg7.(1).cnf
db|verilog_seg7.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
segmain.v
d4976f6fc7c3841899d48f317b6a739
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
segmain:inst1
}
# end
# entity
lpm_counter0
# storage
db|verilog_seg7.(2).cnf
db|verilog_seg7.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
lpm_counter0.vhd
d22f388a2723154a6dc6e41dae0aaae
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
lpm_counter0:inst4
}
# end
# entity
lpm_counter
# storage
db|verilog_seg7.(3).cnf
db|verilog_seg7.(3).cnf
# case_insensitive
# source_file
..|altera|quartus51|libraries|megafunctions|lpm_counter.tdf
a52725e432c6afb55468eb62553a3d9e
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
26
PARAMETER_DEC
USR
LPM_DIRECTION
UP
PARAMETER_UNKNOWN
USR
LPM_MODULUS
0
PARAMETER_UNKNOWN
DEF
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
MAX II
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_mad
PARAMETER_UNKNOWN
USR
}
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q25
-1
3
q24
-1
3
q23
-1
3
q22
-1
3
q21
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# include_file {
..|altera|quartus51|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
..|altera|quartus51|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|altera|quartus51|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
..|altera|quartus51|libraries|megafunctions|cmpconst.inc
e61874547688138e6fc0b49ff8760
..|altera|quartus51|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
..|altera|quartus51|libraries|megafunctions|lpm_counter.inc
758886b0947dd67e65ec58adda9b948
..|altera|quartus51|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
..|altera|quartus51|libraries|megafunctions|alt_synch_counter.inc
e64d362a7450ad9895aa7e1e5dc2b42a
..|altera|quartus51|libraries|megafunctions|alt_synch_counter_f.inc
88e2e3ac71decf106c8d913bf441832f
..|altera|quartus51|libraries|megafunctions|alt_counter_f10ke.inc
d8a92a43831e9df2804dcf9a927e20
..|altera|quartus51|libraries|megafunctions|alt_counter_stratix.inc
587bf41cd15486161ec3eb5a1fef4c2
..|altera|quartus51|libraries|megafunctions|aglobal51.inc
c49d61e8168d42962ec885e3e17640c2
}
# hierarchies {
lpm_counter0:inst4|lpm_counter:lpm_counter_component
}
# end
# entity
cntr_mad
# storage
db|verilog_seg7.(4).cnf
db|verilog_seg7.(4).cnf
# case_insensitive
# source_file
db|cntr_mad.tdf
d46f82a6607aaa0bbdae1f098167357
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q25
-1
3
q24
-1
3
q23
-1
3
q22
-1
3
q21
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# hierarchies {
lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated
}
# end
# entity
subcont
# storage
db|verilog_seg7.(5).cnf
db|verilog_seg7.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
subcont.v
51c9ba63fb5495fdec9fb31677aca4
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
subcont:inst5
}
# end
# entity
addcont
# storage
db|verilog_seg7.(6).cnf
db|verilog_seg7.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
addcont.v
c8884bb60d6dc2e5bfe790b757ae28
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
addcont:inst
}
# end
# entity
bin27seg
# storage
db|verilog_seg7.(7).cnf
db|verilog_seg7.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
bin27seg.v
205aeb583d0b6d25238e196a68a6bb8
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
bin27seg:inst6
}
# end
# complete