verilog_seg7.map.summary

Verilog 经典实例

Analysis & Synthesis Status : Successful - Sun Nov 19 23:21:26 2006
Quartus II Version : 5.1 Build 216 03/06/2006 SP 2 SJ Full Version
Revision Name : verilog_seg7
Top-level Entity Name : verilog_seg7
Family : MAX II
Total logic elements : 62
Total pins : 13
Total virtual pins : 0
UFM blocks : 0