verilog_seg7.fit.summary

Verilog 经典实例

Fitter Status : Successful - Sun Nov 19 23:21:41 2006
Quartus II Version : 5.1 Build 216 03/06/2006 SP 2 SJ Full Version
Revision Name : verilog_seg7
Top-level Entity Name : verilog_seg7
Family : MAX II
Device : EPM1270T144C5
Timing Models : Final
Total logic elements : 62 / 1,270 ( 5 % )
Total pins : 13 / 116 ( 11 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )