cntr_peh.tdf

Verilog 经典实例

--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=16 clock q CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 7.2 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_counter 2007:08:07:01:40:08:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION cyclone_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( cin0_used, cin1_used, cin_used, lut_mask, operation_mode, output_mode, power_up, register_cascade_mode, sum_lutc_input, synch_mode, x_on_violation)
RETURNS ( combout, cout, regout);

--synthesis_resources = lut 16 
SUBDESIGN cntr_peh
( 
	clock	:	input;
	q[15..0]	:	output;
) 
VARIABLE 
	counter_cella0 : cyclone_lcell
		WITH (
			cin_used = "false",
			lut_mask = "11AA",
			operation_mode = "arithmetic",
			synch_mode = "on"
		);
	counter_cella1 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella2 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella3 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella4 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella5 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella6 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella7 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella8 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella9 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella10 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella11 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella12 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella13 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella14 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella15 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "normal",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	aclr	: NODE;
	aclr_actual	: WIRE;
	clk_en	: NODE;
	data[15..0]	: NODE;
	safe_q[15..0]	: WIRE;
	sclr	: NODE;
	sload	: NODE;

BEGIN 
	counter_cella[15..0].aclr = aclr_actual;
	counter_cella[15..0].aload = B"0000000000000000";
	counter_cella[1].cin = counter_cella[0].cout;
	counter_cella[2].cin = counter_cella[1].cout;
	counter_cella[3].cin = counter_cella[2].cout;
	counter_cella[4].cin = counter_cella[3].cout;
	counter_cella[5].cin = counter_cella[4].cout;
	counter_cella[6].cin = counter_cella[5].cout;
	counter_cella[7].cin = counter_cella[6].cout;
	counter_cella[8].cin = counter_cella[7].cout;
	counter_cella[9].cin = counter_cella[8].cout;
	counter_cella[10].cin = counter_cella[9].cout;
	counter_cella[11].cin = counter_cella[10].cout;
	counter_cella[12].cin = counter_cella[11].cout;
	counter_cella[13].cin = counter_cella[12].cout;
	counter_cella[14].cin = counter_cella[13].cout;
	counter_cella[15].cin = counter_cella[14].cout;
	counter_cella[15..0].clk = clock;
	counter_cella[15..0].dataa = safe_q[];
	counter_cella[15..0].datab = B"0000000000000000";
	counter_cella[15..0].datac = data[];
	counter_cella[15].datad = B"1";
	counter_cella[15..0].ena = clk_en;
	counter_cella[15..0].sclr = sclr;
	counter_cella[15..0].sload = sload;
	aclr = GND;
	aclr_actual = aclr;
	clk_en = VCC;
	data[] = GND;
	q[] = safe_q[];
	safe_q[] = counter_cella[15..0].regout;
	sclr = GND;
	sload = GND;
END;
--VALID FILE