seg7led.fnsim.qmsg

Verilog 经典实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 28 17:56:32 2007 " "Info: Processing started: Fri Dec 28 17:56:32 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off seg7led -c seg7led --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seg7led -c seg7led --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7led.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file seg7led.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 seg7led " "Info: Found entity 1: seg7led" {  } { { "seg7led.bdf" "" { Schematic "G:/Q71/verilog/seg7led/seg7led.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int_div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file int_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 int_div-behav " "Info: Found design unit 1: int_div-behav" {  } { { "int_div.vhd" "" { Text "G:/Q71/verilog/seg7led/int_div.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 int_div " "Info: Found entity 1: int_div" {  } { { "int_div.vhd" "" { Text "G:/Q71/verilog/seg7led/int_div.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "segmain.v(14) " "Warning (10268): Verilog HDL information at segmain.v(14): Always Construct contains both blocking and non-blocking assignments" {  } { { "segmain.v" "" { Text "G:/Q71/verilog/seg7led/segmain.v" 14 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "segmain.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file segmain.v" { { "Info" "ISGN_ENTITY_NAME" "1 segmain " "Info: Found entity 1: segmain" {  } { { "segmain.v" "" { Text "G:/Q71/verilog/seg7led/segmain.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "segmain " "Info: Elaborating entity \"segmain\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "5 " "Info: Inferred 5 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" {  } { { "segmain.v" "Add0" { Text "G:/Q71/verilog/seg7led/segmain.v" 19 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux0\"" {  } { { "segmain.v" "Mux0" { Text "G:/Q71/verilog/seg7led/segmain.v" 24 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux1\"" {  } { { "segmain.v" "Mux1" { Text "G:/Q71/verilog/seg7led/segmain.v" 24 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux2\"" {  } { { "segmain.v" "Mux2" { Text "G:/Q71/verilog/seg7led/segmain.v" 24 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux3\"" {  } { { "segmain.v" "Mux3" { Text "G:/Q71/verilog/seg7led/segmain.v" 24 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "g:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "segmain.v" "" { Text "G:/Q71/verilog/seg7led/segmain.v" 19 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/72/quartus/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "g:/altera/72/quartus/libraries/megafunctions/addcore.tdf" 76 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "g:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "segmain.v" "" { Text "G:/Q71/verilog/seg7led/segmain.v" 19 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 37 " "Info: Parameter \"LPM_WIDTH\" = \"37\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "segmain.v" "" { Text "G:/Q71/verilog/seg7led/segmain.v" 19 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "g:/altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}