seg7led.hier_info

Verilog 经典实例

|seg7led
78ledcom[0] <= segmain:inst1.seg_com[0]
78ledcom[1] <= segmain:inst1.seg_com[1]
78ledcom[2] <= segmain:inst1.seg_com[2]
78ledcom[3] <= segmain:inst1.seg_com[3]
clk => segmain:inst1.clk
clk => int_div:inst6.clk
reset => segmain:inst1.reset_n
reset => inst3.IN0
78leddata[0] <= segmain:inst1.seg_data[0]
78leddata[1] <= segmain:inst1.seg_data[1]
78leddata[2] <= segmain:inst1.seg_data[2]
78leddata[3] <= segmain:inst1.seg_data[3]
78leddata[4] <= segmain:inst1.seg_data[4]
78leddata[5] <= segmain:inst1.seg_data[5]
78leddata[6] <= segmain:inst1.seg_data[6]
78leddata[7] <= segmain:inst1.seg_data[7]


|seg7led|segmain:inst1
clk => count[36].CLK
clk => count[35].CLK
clk => count[34].CLK
clk => count[33].CLK
clk => count[32].CLK
clk => count[31].CLK
clk => count[30].CLK
clk => count[29].CLK
clk => count[28].CLK
clk => count[27].CLK
clk => count[26].CLK
clk => count[25].CLK
clk => count[24].CLK
clk => count[23].CLK
clk => count[22].CLK
clk => count[21].CLK
clk => count[20].CLK
clk => count[19].CLK
clk => count[18].CLK
clk => count[17].CLK
clk => count[16].CLK
clk => count[15].CLK
clk => count[14].CLK
clk => count[13].CLK
clk => count[12].CLK
clk => count[11].CLK
clk => count[10].CLK
clk => count[9].CLK
clk => count[8].CLK
clk => count[7].CLK
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
reset_n => count~36.OUTPUTSELECT
reset_n => count~35.OUTPUTSELECT
reset_n => count~34.OUTPUTSELECT
reset_n => count~33.OUTPUTSELECT
reset_n => count~32.OUTPUTSELECT
reset_n => count~31.OUTPUTSELECT
reset_n => count~30.OUTPUTSELECT
reset_n => count~29.OUTPUTSELECT
reset_n => count~28.OUTPUTSELECT
reset_n => count~27.OUTPUTSELECT
reset_n => count~26.OUTPUTSELECT
reset_n => count~25.OUTPUTSELECT
reset_n => count~24.OUTPUTSELECT
reset_n => count~23.OUTPUTSELECT
reset_n => count~22.OUTPUTSELECT
reset_n => count~21.OUTPUTSELECT
reset_n => count~20.OUTPUTSELECT
reset_n => count~19.OUTPUTSELECT
reset_n => count~18.OUTPUTSELECT
reset_n => count~17.OUTPUTSELECT
reset_n => count~16.OUTPUTSELECT
reset_n => count~15.OUTPUTSELECT
reset_n => count~14.OUTPUTSELECT
reset_n => count~13.OUTPUTSELECT
reset_n => count~12.OUTPUTSELECT
reset_n => count~11.OUTPUTSELECT
reset_n => count~10.OUTPUTSELECT
reset_n => count~9.OUTPUTSELECT
reset_n => count~8.OUTPUTSELECT
reset_n => count~7.OUTPUTSELECT
reset_n => count~6.OUTPUTSELECT
reset_n => count~5.OUTPUTSELECT
reset_n => count~4.OUTPUTSELECT
reset_n => count~3.OUTPUTSELECT
reset_n => count~2.OUTPUTSELECT
reset_n => count~1.OUTPUTSELECT
reset_n => count~0.OUTPUTSELECT
datain[0] => Mux3.IN3
datain[1] => Mux2.IN3
datain[2] => Mux1.IN3
datain[3] => Mux0.IN3
datain[4] => Mux3.IN2
datain[5] => Mux2.IN2
datain[6] => Mux1.IN2
datain[7] => Mux0.IN2
datain[8] => Mux3.IN1
datain[9] => Mux2.IN1
datain[10] => Mux1.IN1
datain[11] => Mux0.IN1
datain[12] => Mux3.IN0
datain[13] => Mux2.IN0
datain[14] => Mux1.IN0
datain[15] => Mux0.IN0
seg_data[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
seg_data[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
seg_data[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
seg_data[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
seg_data[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
seg_data[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
seg_data[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
seg_data[7] <= <VCC>
seg_com[0] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
seg_com[1] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
seg_com[2] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
seg_com[3] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE


|seg7led|lpm_counter0:inst
clock => clock~0.IN1
sclr => sclr~0.IN1
q[0] <= lpm_counter:lpm_counter_component.q
q[1] <= lpm_counter:lpm_counter_component.q
q[2] <= lpm_counter:lpm_counter_component.q
q[3] <= lpm_counter:lpm_counter_component.q
q[4] <= lpm_counter:lpm_counter_component.q
q[5] <= lpm_counter:lpm_counter_component.q
q[6] <= lpm_counter:lpm_counter_component.q
q[7] <= lpm_counter:lpm_counter_component.q
q[8] <= lpm_counter:lpm_counter_component.q
q[9] <= lpm_counter:lpm_counter_component.q
q[10] <= lpm_counter:lpm_counter_component.q
q[11] <= lpm_counter:lpm_counter_component.q
q[12] <= lpm_counter:lpm_counter_component.q
q[13] <= lpm_counter:lpm_counter_component.q
q[14] <= lpm_counter:lpm_counter_component.q
q[15] <= lpm_counter:lpm_counter_component.q


|seg7led|lpm_counter0:inst|lpm_counter:lpm_counter_component
clock => cntr_dth:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => cntr_dth:auto_generated.sclr
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
data[12] => ~NO_FANOUT~
data[13] => ~NO_FANOUT~
data[14] => ~NO_FANOUT~
data[15] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_dth:auto_generated.q[0]
q[1] <= cntr_dth:auto_generated.q[1]
q[2] <= cntr_dth:auto_generated.q[2]
q[3] <= cntr_dth:auto_generated.q[3]
q[4] <= cntr_dth:auto_generated.q[4]
q[5] <= cntr_dth:auto_generated.q[5]
q[6] <= cntr_dth:auto_generated.q[6]
q[7] <= cntr_dth:auto_generated.q[7]
q[8] <= cntr_dth:auto_generated.q[8]
q[9] <= cntr_dth:auto_generated.q[9]
q[10] <= cntr_dth:auto_generated.q[10]
q[11] <= cntr_dth:auto_generated.q[11]
q[12] <= cntr_dth:auto_generated.q[12]
q[13] <= cntr_dth:auto_generated.q[13]
q[14] <= cntr_dth:auto_generated.q[14]
q[15] <= cntr_dth:auto_generated.q[15]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|seg7led|lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
clock => counter_cella12.CLK
clock => counter_cella13.CLK
clock => counter_cella14.CLK
clock => counter_cella15.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT
q[12] <= counter_cella12.REGOUT
q[13] <= counter_cella13.REGOUT
q[14] <= counter_cella14.REGOUT
q[15] <= counter_cella15.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR
sclr => counter_cella4.SCLR
sclr => counter_cella5.SCLR
sclr => counter_cella6.SCLR
sclr => counter_cella7.SCLR
sclr => counter_cella8.SCLR
sclr => counter_cella9.SCLR
sclr => counter_cella10.SCLR
sclr => counter_cella11.SCLR
sclr => counter_cella12.SCLR
sclr => counter_cella13.SCLR
sclr => counter_cella14.SCLR
sclr => counter_cella15.SCLR


|seg7led|int_div:inst6
clk => clk_div[31].CLK
clk => clk_div[30].CLK
clk => clk_div[29].CLK
clk => clk_div[28].CLK
clk => clk_div[27].CLK
clk => clk_div[26].CLK
clk => clk_div[25].CLK
clk => clk_div[24].CLK
clk => clk_div[23].CLK
clk => clk_div[22].CLK
clk => clk_div[21].CLK
clk => clk_div[20].CLK
clk => clk_div[19].CLK
clk => clk_div[18].CLK
clk => clk_div[17].CLK
clk => clk_div[16].CLK
clk => clk_div[15].CLK
clk => clk_div[14].CLK
clk => clk_div[13].CLK
clk => clk_div[12].CLK
clk => clk_div[11].CLK
clk => clk_div[10].CLK
clk => clk_div[9].CLK
clk => clk_div[8].CLK
clk => clk_div[7].CLK
clk => clk_div[6].CLK
clk => clk_div[5].CLK
clk => clk_div[4].CLK
clk => clk_div[3].CLK
clk => clk_div[2].CLK
clk => clk_div[1].CLK
clk => clk_div[0].CLK
clk => div_out~reg0.CLK
div_out <= div_out~reg0.DB_MAX_OUTPUT_PORT_TYPE