seg7led.tan.summary

Verilog 经典实例

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 8.643 ns
From           : reset
To             : segmain:inst1|count[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.319 ns
From           : lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[7]
To             : 78leddata[3]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.465 ns
From           : reset
To             : lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[15]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 161.76 MHz ( period = 6.182 ns )
From           : int_div:inst6|clk_div[23]
To             : int_div:inst6|clk_div[1]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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