int_div.v

Verilog 经典实例

module int_div(clk,div_out);

input clk;
output reg div_out;

reg [31:0] clk_div;

parameter CLK_FREQ = 'D50_000_000;//系统时钟
parameter DCLK_FREQ = 'D10;        //输出频率10Hz

always @(posedge clk)
begin
 if(clk_div<(CLK_FREQ/DCLK_FREQ))
    clk_div <= clk_div + 1;
  else
   begin
   clk_div <= 0;
   div_out <= ~div_out;
   end
end

endmodule