seg7led.fit.summary

来自「Verilog 经典实例」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Fri Dec 28 21:56:43 2007
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : seg7led
Top-level Entity Name : seg7led
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 92 / 5,980 ( 2 % )
Total pins : 14 / 185 ( 8 % )
Total virtual pins : 0
Total memory bits : 0 / 92,160 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )