seg7led.qsf

Verilog 经典实例

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		seg7led_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY seg7led
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:29:22  NOVEMBER 28, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name BDF_FILE seg7led.bdf
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name TCL_SCRIPT_FILE setup.tcl
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
set_location_assignment PIN_28 -to clk
set_location_assignment PIN_61 -to reset
set_location_assignment PIN_165 -to 78ledcom[0]
set_location_assignment PIN_164 -to 78ledcom[1]
set_location_assignment PIN_167 -to 78ledcom[2]
set_location_assignment PIN_166 -to 78ledcom[3]
set_location_assignment PIN_162 -to 78leddata[0]
set_location_assignment PIN_160 -to 78leddata[1]
set_location_assignment PIN_156 -to 78leddata[2]
set_location_assignment PIN_158 -to 78leddata[3]
set_location_assignment PIN_161 -to 78leddata[4]
set_location_assignment PIN_163 -to 78leddata[5]
set_location_assignment PIN_144 -to 78leddata[6]
set_location_assignment PIN_159 -to 78leddata[7]
set_global_assignment -name VECTOR_WAVEFORM_FILE seg7led.vwf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name END_TIME "1 s"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_FILE segmain.v
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE seg7led.vwf
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING ALWAYS
set_global_assignment -name VERILOG_FILE int_div.v
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top