vga.tan.qmsg

Verilog 经典实例

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "VGA.bdf" "" { Schematic "D:/Verilog_VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "reset " "Info: Assuming node \"reset\" is an undefined clock" {  } { { "VGA.bdf" "" { Schematic "D:/Verilog_VGA/VGA.bdf" { { 168 -16 152 184 "reset" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "VGAsignal:inst1\|FS\[5\] " "Info: Detected ripple clock \"VGAsignal:inst1\|FS\[5\]\" as buffer" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 19 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsignal:inst1\|FS\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "VGAsignal:inst1\|CC\[4\] " "Info: Detected ripple clock \"VGAsignal:inst1\|CC\[4\]\" as buffer" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 63 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsignal:inst1\|CC\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register VGAsignal:inst1\|LL\[2\] register VGAsignal:inst1\|LL\[7\] 132.86 MHz 7.527 ns Internal " "Info: Clock \"clk\" has Internal fmax of 132.86 MHz between source register \"VGAsignal:inst1\|LL\[2\]\" and destination register \"VGAsignal:inst1\|LL\[7\]\" (period= 7.527 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.818 ns + Longest register register " "Info: + Longest register to register delay is 6.818 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsignal:inst1\|LL\[2\] 1 REG LC_X14_Y7_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y7_N2; Fanout = 6; REG Node = 'VGAsignal:inst1\|LL\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "" { VGAsignal:inst1|LL[2] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.043 ns) + CELL(0.747 ns) 2.790 ns VGAsignal:inst1\|add~381 2 COMB LC_X12_Y7_N2 2 " "Info: 2: + IC(2.043 ns) + CELL(0.747 ns) = 2.790 ns; Loc. = LC_X12_Y7_N2; Fanout = 2; COMB Node = 'VGAsignal:inst1\|add~381'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "2.790 ns" { VGAsignal:inst1|LL[2] VGAsignal:inst1|add~381 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.913 ns VGAsignal:inst1\|add~351 3 COMB LC_X12_Y7_N3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.913 ns; Loc. = LC_X12_Y7_N3; Fanout = 2; COMB Node = 'VGAsignal:inst1\|add~351'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "0.123 ns" { VGAsignal:inst1|add~381 VGAsignal:inst1|add~351 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 3.174 ns VGAsignal:inst1\|add~341 4 COMB LC_X12_Y7_N4 4 " "Info: 4: + IC(0.000 ns) + CELL(0.261 ns) = 3.174 ns; Loc. = LC_X12_Y7_N4; Fanout = 4; COMB Node = 'VGAsignal:inst1\|add~341'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "0.261 ns" { VGAsignal:inst1|add~351 VGAsignal:inst1|add~341 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 4.149 ns VGAsignal:inst1\|add~344 5 COMB LC_X12_Y7_N7 1 " "Info: 5: + IC(0.000 ns) + CELL(0.975 ns) = 4.149 ns; Loc. = LC_X12_Y7_N7; Fanout = 1; COMB Node = 'VGAsignal:inst1\|add~344'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "0.975 ns" { VGAsignal:inst1|add~341 VGAsignal:inst1|add~344 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.865 ns) + CELL(0.804 ns) 6.818 ns VGAsignal:inst1\|LL\[7\] 6 REG LC_X14_Y7_N5 10 " "Info: 6: + IC(1.865 ns) + CELL(0.804 ns) = 6.818 ns; Loc. = LC_X14_Y7_N5; Fanout = 10; REG Node = 'VGAsignal:inst1\|LL\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "2.669 ns" { VGAsignal:inst1|add~344 VGAsignal:inst1|LL[7] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.910 ns ( 42.68 % ) " "Info: Total cell delay = 2.910 ns ( 42.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.908 ns ( 57.32 % ) " "Info: Total interconnect delay = 3.908 ns ( 57.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "6.818 ns" { VGAsignal:inst1|LL[2] VGAsignal:inst1|add~381 VGAsignal:inst1|add~351 VGAsignal:inst1|add~341 VGAsignal:inst1|add~344 VGAsignal:inst1|LL[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.818 ns" { VGAsignal:inst1|LL[2] VGAsignal:inst1|add~381 VGAsignal:inst1|add~351 VGAsignal:inst1|add~341 VGAsignal:inst1|add~344 VGAsignal:inst1|LL[7] } { 0.000ns 2.043ns 0.000ns 0.000ns 0.000ns 1.865ns } { 0.000ns 0.747ns 0.123ns 0.261ns 0.975ns 0.804ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.368 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 13.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "" { clk } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "D:/Verilog_VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns VGAsignal:inst1\|FS\[5\] 2 REG LC_X12_Y4_N0 7 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y4_N0; Fanout = 7; REG Node = 'VGAsignal:inst1\|FS\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "3.032 ns" { clk VGAsignal:inst1|FS[5] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.933 ns) + CELL(1.294 ns) 9.422 ns VGAsignal:inst1\|CC\[4\] 3 REG LC_X12_Y3_N1 15 " "Info: 3: + IC(3.933 ns) + CELL(1.294 ns) = 9.422 ns; Loc. = LC_X12_Y3_N1; Fanout = 15; REG Node = 'VGAsignal:inst1\|CC\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "5.227 ns" { VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(0.918 ns) 13.368 ns VGAsignal:inst1\|LL\[7\] 4 REG LC_X14_Y7_N5 10 " "Info: 4: + IC(3.028 ns) + CELL(0.918 ns) = 13.368 ns; Loc. = LC_X14_Y7_N5; Fanout = 10; REG Node = 'VGAsignal:inst1\|LL\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "3.946 ns" { VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[7] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 34.93 % ) " "Info: Total cell delay = 4.669 ns ( 34.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.699 ns ( 65.07 % ) " "Info: Total interconnect delay = 8.699 ns ( 65.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "13.368 ns" { clk VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.368 ns" { clk clk~combout VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[7] } { 0.000ns 0.000ns 1.738ns 3.933ns 3.028ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.368 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 13.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "" { clk } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "D:/Verilog_VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns VGAsignal:inst1\|FS\[5\] 2 REG LC_X12_Y4_N0 7 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y4_N0; Fanout = 7; REG Node = 'VGAsignal:inst1\|FS\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "3.032 ns" { clk VGAsignal:inst1|FS[5] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.933 ns) + CELL(1.294 ns) 9.422 ns VGAsignal:inst1\|CC\[4\] 3 REG LC_X12_Y3_N1 15 " "Info: 3: + IC(3.933 ns) + CELL(1.294 ns) = 9.422 ns; Loc. = LC_X12_Y3_N1; Fanout = 15; REG Node = 'VGAsignal:inst1\|CC\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "5.227 ns" { VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(0.918 ns) 13.368 ns VGAsignal:inst1\|LL\[2\] 4 REG LC_X14_Y7_N2 6 " "Info: 4: + IC(3.028 ns) + CELL(0.918 ns) = 13.368 ns; Loc. = LC_X14_Y7_N2; Fanout = 6; REG Node = 'VGAsignal:inst1\|LL\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "3.946 ns" { VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[2] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 34.93 % ) " "Info: Total cell delay = 4.669 ns ( 34.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.699 ns ( 65.07 % ) " "Info: Total interconnect delay = 8.699 ns ( 65.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "13.368 ns" { clk VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.368 ns" { clk clk~combout VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[2] } { 0.000ns 0.000ns 1.738ns 3.933ns 3.028ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "13.368 ns" { clk VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.368 ns" { clk clk~combout VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[7] } { 0.000ns 0.000ns 1.738ns 3.933ns 3.028ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "13.368 ns" { clk VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.368 ns" { clk clk~combout VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[2] } { 0.000ns 0.000ns 1.738ns 3.933ns 3.028ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 73 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 73 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "6.818 ns" { VGAsignal:inst1|LL[2] VGAsignal:inst1|add~381 VGAsignal:inst1|add~351 VGAsignal:inst1|add~341 VGAsignal:inst1|add~344 VGAsignal:inst1|LL[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.818 ns" { VGAsignal:inst1|LL[2] VGAsignal:inst1|add~381 VGAsignal:inst1|add~351 VGAsignal:inst1|add~341 VGAsignal:inst1|add~344 VGAsignal:inst1|LL[7] } { 0.000ns 2.043ns 0.000ns 0.000ns 0.000ns 1.865ns } { 0.000ns 0.747ns 0.123ns 0.261ns 0.975ns 0.804ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "13.368 ns" { clk VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.368 ns" { clk clk~combout VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[7] } { 0.000ns 0.000ns 1.738ns 3.933ns 3.028ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "13.368 ns" { clk VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.368 ns" { clk clk~combout VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[2] } { 0.000ns 0.000ns 1.738ns 3.933ns 3.028ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}