vga.fit.qmsg

Verilog 经典实例

{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0 0 "Moving registers into LUTs to improve timing and density" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0 0 "Finished moving registers into LUTs" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Info: Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "11.263 ns register pin " "Info: Estimated most critical path is register to pin delay of 11.263 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsignal:inst1\|LL\[6\] 1 REG LAB_X13_Y7 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y7; Fanout = 10; REG Node = 'VGAsignal:inst1\|LL\[6\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "" { VGAsignal:inst1|LL[6] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.978 ns) + CELL(0.914 ns) 1.892 ns VGAsignal:inst1\|GRBY\[2\]~814 2 COMB LAB_X14_Y7 1 " "Info: 2: + IC(0.978 ns) + CELL(0.914 ns) = 1.892 ns; Loc. = LAB_X14_Y7; Fanout = 1; COMB Node = 'VGAsignal:inst1\|GRBY\[2\]~814'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "1.892 ns" { VGAsignal:inst1|LL[6] VGAsignal:inst1|GRBY[2]~814 } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.740 ns) 3.532 ns VGAsignal:inst1\|GRBY\[2\]~815 3 COMB LAB_X13_Y7 1 " "Info: 3: + IC(0.900 ns) + CELL(0.740 ns) = 3.532 ns; Loc. = LAB_X13_Y7; Fanout = 1; COMB Node = 'VGAsignal:inst1\|GRBY\[2\]~815'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "1.640 ns" { VGAsignal:inst1|GRBY[2]~814 VGAsignal:inst1|GRBY[2]~815 } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.914 ns) 4.715 ns VGAsignal:inst1\|GRBY\[2\]~817 4 COMB LAB_X13_Y7 1 " "Info: 4: + IC(0.269 ns) + CELL(0.914 ns) = 4.715 ns; Loc. = LAB_X13_Y7; Fanout = 1; COMB Node = 'VGAsignal:inst1\|GRBY\[2\]~817'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "1.183 ns" { VGAsignal:inst1|GRBY[2]~815 VGAsignal:inst1|GRBY[2]~817 } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.914 ns) 5.898 ns VGAsignal:inst1\|GRBP\[2\]~752 5 COMB LAB_X13_Y7 1 " "Info: 5: + IC(0.269 ns) + CELL(0.914 ns) = 5.898 ns; Loc. = LAB_X13_Y7; Fanout = 1; COMB Node = 'VGAsignal:inst1\|GRBP\[2\]~752'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "1.183 ns" { VGAsignal:inst1|GRBY[2]~817 VGAsignal:inst1|GRBP[2]~752 } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.740 ns) 7.081 ns VGAsignal:inst1\|R 6 COMB LAB_X13_Y7 1 " "Info: 6: + IC(0.443 ns) + CELL(0.740 ns) = 7.081 ns; Loc. = LAB_X13_Y7; Fanout = 1; COMB Node = 'VGAsignal:inst1\|R'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "1.183 ns" { VGAsignal:inst1|GRBP[2]~752 VGAsignal:inst1|R } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.860 ns) + CELL(2.322 ns) 11.263 ns r 7 PIN PIN_112 0 " "Info: 7: + IC(1.860 ns) + CELL(2.322 ns) = 11.263 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'r'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "4.182 ns" { VGAsignal:inst1|R r } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "D:/Verilog_VGA/VGA.bdf" { { 160 464 640 176 "r" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.544 ns ( 58.10 % ) " "Info: Total cell delay = 6.544 ns ( 58.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.719 ns ( 41.90 % ) " "Info: Total interconnect delay = 4.719 ns ( 41.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "11.263 ns" { VGAsignal:inst1|LL[6] VGAsignal:inst1|GRBY[2]~814 VGAsignal:inst1|GRBY[2]~815 VGAsignal:inst1|GRBY[2]~817 VGAsignal:inst1|GRBP[2]~752 VGAsignal:inst1|R r } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." {  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 19 23:32:13 2006 " "Info: Processing ended: Sun Nov 19 23:32:13 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}