vga.map.qmsg

Verilog 经典实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 19 23:31:52 2006 " "Info: Processing started: Sun Nov 19 23:31:52 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGA.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file VGA.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 VGA " "Info: Found entity 1: VGA" {  } { { "VGA.bdf" "" { Schematic "D:/Verilog_VGA/VGA.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "VGAsignal.v(75) " "Warning (10268): Verilog HDL information at VGAsignal.v(75): Always Construct contains both blocking and non-blocking assignments" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 75 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGAsignal.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file VGAsignal.v" { { "Info" "ISGN_ENTITY_NAME" "1 VGAsignal " "Info: Found entity 1: VGAsignal" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "VGA " "Info: Elaborating entity \"VGA\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGAsignal VGAsignal:inst1 " "Info: Elaborating entity \"VGAsignal\" for hierarchy \"VGAsignal:inst1\"" {  } { { "VGA.bdf" "inst1" { Schematic "D:/Verilog_VGA/VGA.bdf" { { 104 280 376 232 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 VGAsignal.v(35) " "Warning (10230): Verilog HDL assignment warning at VGAsignal.v(35): truncated value with size 32 to match size of target (2)" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 35 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "GRBX VGAsignal.v(41) " "Warning (10235): Verilog HDL Always Construct warning at VGAsignal.v(41): variable \"GRBX\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 41 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "GRBY VGAsignal.v(42) " "Warning (10235): Verilog HDL Always Construct warning at VGAsignal.v(42): variable \"GRBY\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 42 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "GRBX VGAsignal.v(43) " "Warning (10235): Verilog HDL Always Construct warning at VGAsignal.v(43): variable \"GRBX\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 43 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "GRBY VGAsignal.v(43) " "Warning (10235): Verilog HDL Always Construct warning at VGAsignal.v(43): variable \"GRBY\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 43 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 VGAsignal.v(51) " "Warning (10230): Verilog HDL assignment warning at VGAsignal.v(51): truncated value with size 32 to match size of target (6)" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 51 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 VGAsignal.v(61) " "Warning (10230): Verilog HDL assignment warning at VGAsignal.v(61): truncated value with size 32 to match size of target (5)" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 61 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 VGAsignal.v(71) " "Warning (10230): Verilog HDL assignment warning at VGAsignal.v(71): truncated value with size 32 to match size of target (9)" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "77 " "Info: Implemented 77 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "70 " "Info: Implemented 70 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 19 23:32:01 2006 " "Info: Processing ended: Sun Nov 19 23:32:01 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}