serial_verilog.tan.summary

来自「Verilog 经典实例」· SUMMARY 代码 · 共 37 行

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.539 ns
From           : serial:inst|txd_reg
To             : txd_usb
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 119.89 MHz ( period = 8.341 ns )
From           : serial:inst|div_reg[1]
To             : serial:inst|div_reg[15]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------