serial_verilog.hier_info

Verilog 经典实例

|serial_verilog
txd_usb <= serial:inst.txd
clk => serial:inst.clk
reset => serial:inst.rst
rxd_usb => serial:inst.rxd


|serial_verilog|serial:inst
clk => div_reg[14].CLK
clk => div_reg[13].CLK
clk => div_reg[12].CLK
clk => div_reg[11].CLK
clk => div_reg[10].CLK
clk => div_reg[9].CLK
clk => div_reg[8].CLK
clk => div_reg[7].CLK
clk => div_reg[6].CLK
clk => div_reg[5].CLK
clk => div_reg[4].CLK
clk => div_reg[3].CLK
clk => div_reg[2].CLK
clk => div_reg[1].CLK
clk => div_reg[0].CLK
clk => clkbaud8x.CLK
clk => div_reg[15].CLK
rst => trasstart.ACLR
rst => txd_buf[7].ACLR
rst => txd_buf[6].PRESET
rst => txd_buf[5].PRESET
rst => txd_buf[4].PRESET
rst => txd_buf[3].ACLR
rst => txd_buf[2].PRESET
rst => txd_buf[1].PRESET
rst => txd_buf[0].PRESET
rst => state_tras[3].ACLR
rst => state_tras[2].ACLR
rst => state_tras[1].ACLR
rst => state_tras[0].ACLR
rst => send_state[2].ACLR
rst => send_state[1].ACLR
rst => send_state[0].ACLR
rst => div_reg[14].ACLR
rst => div_reg[13].ACLR
rst => txd_reg.PRESET
rst => div_reg[12].ACLR
rst => div_reg[11].ACLR
rst => div_reg[10].ACLR
rst => div_reg[9].ACLR
rst => div_reg[8].ACLR
rst => div_reg[7].ACLR
rst => div_reg[6].ACLR
rst => div_reg[5].ACLR
rst => div_reg[4].ACLR
rst => div_reg[3].ACLR
rst => div_reg[2].ACLR
rst => div_reg[1].ACLR
rst => div_reg[0].ACLR
rst => clkbaud8x.ACLR
rst => div_reg[15].ACLR
rst => div8_tras_reg[1].ACLR
rst => div8_tras_reg[0].ACLR
rst => div8_tras_reg[2].ACLR
rxd => ~NO_FANOUT~
txd <= txd_reg.DB_MAX_OUTPUT_PORT_TYPE