serial_verilog.map.qmsg

Verilog 经典实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 19 22:42:39 2006 " "Info: Processing started: Sun Nov 19 22:42:39 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off serial_verilog -c serial_verilog " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serial_verilog -c serial_verilog" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serial_verilog.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file serial_verilog.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 serial_verilog " "Info: Found entity 1: serial_verilog" {  } { { "serial_verilog.bdf" "" { Schematic "D:/Test/serial_verilog/serial_verilog.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "serial.v(99) " "Warning (10268): Verilog HDL information at serial.v(99): Always Construct contains both blocking and non-blocking assignments" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 99 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 0 0}
{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "serial serial.v(19) " "Warning (10238): Verilog Module Declaration warning at serial.v(19): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"serial\"" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 19 0 0 } }  } 0 10238 "Verilog Module Declaration warning at %2!s!: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serial.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file serial.v" { { "Info" "ISGN_ENTITY_NAME" "1 serial " "Info: Found entity 1: serial" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 14 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "serial_verilog " "Info: Elaborating entity \"serial_verilog\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "serial serial:inst " "Info: Elaborating entity \"serial\" for hierarchy \"serial:inst\"" {  } { { "serial_verilog.bdf" "inst" { Schematic "D:/Test/serial_verilog/serial_verilog.bdf" { { 128 240 336 224 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "rxd serial.v(22) " "Info (10035): Verilog HDL or VHDL information at serial.v(22): object \"rxd\" declared but not used" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 22 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "state_rec serial.v(30) " "Info (10035): Verilog HDL or VHDL information at serial.v(30): object \"state_rec\" declared but not used" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 30 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "clkbaud_rec serial.v(32) " "Warning (10036): Verilog HDL or VHDL warning at serial.v(32): object \"clkbaud_rec\" assigned a value but never read" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 32 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "recstart_tmp serial.v(35) " "Info (10035): Verilog HDL or VHDL information at serial.v(35): object \"recstart_tmp\" declared but not used" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 35 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "rxd_reg1 serial.v(37) " "Info (10035): Verilog HDL or VHDL information at serial.v(37): object \"rxd_reg1\" declared but not used" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 37 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "rxd_reg2 serial.v(38) " "Info (10035): Verilog HDL or VHDL information at serial.v(38): object \"rxd_reg2\" declared but not used" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 38 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "rxd_buf serial.v(40) " "Info (10035): Verilog HDL or VHDL information at serial.v(40): object \"rxd_buf\" declared but not used" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 40 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "key_entry2 serial.v(43) " "Warning (10036): Verilog HDL or VHDL warning at serial.v(43): object \"key_entry2\" assigned a value but never read" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 43 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "div8_tras_reg serial.v(93) " "Warning (10235): Verilog HDL Always Construct warning at serial.v(93): variable \"div8_tras_reg\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 93 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "serial:inst\|txd_buf\[7\] data_in GND " "Warning: Reduced register \"serial:inst\|txd_buf\[7\]\" with stuck data_in port to stuck value GND" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 101 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 101 -1 0 } } { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 101 -1 0 } } { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 101 -1 0 } } { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 101 -1 0 } } { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 101 -1 0 } } { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 101 -1 0 } } { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 101 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "rxd_usb " "Warning: No output dependent on input pin \"rxd_usb\"" {  } { { "serial_verilog.bdf" "" { Schematic "D:/Test/serial_verilog/serial_verilog.bdf" { { 184 -8 160 200 "rxd_usb" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "84 " "Info: Implemented 84 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "80 " "Info: Implemented 80 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 19 22:42:47 2006 " "Info: Processing ended: Sun Nov 19 22:42:47 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}