serial_verilog.map.summary

来自「Verilog 经典实例」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Sun Nov 19 22:42:47 2006
Quartus II Version : 5.1 Build 216 03/06/2006 SP 2 SJ Full Version
Revision Name : serial_verilog
Top-level Entity Name : serial_verilog
Family : MAX II
Total logic elements : 80
Total pins : 4
Total virtual pins : 0
UFM blocks : 0