multl6s.tan.qmsg

Verilog 经典实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 15 13:49:40 2007 " "Info: Processing started: Sat Dec 15 13:49:40 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off multl6s -c multl6s --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off multl6s -c multl6s --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "A\[12\] P\[18\] 19.166 ns Longest " "Info: Longest tpd from source pin \"A\[12\]\" to destination pin \"P\[18\]\" is 19.166 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns A\[12\] 1 PIN PIN_117 20 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_117; Fanout = 20; PIN Node = 'A\[12\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { A[12] } "NODE_NAME" } } { "multl6s.bdf" "" { Schematic "G:/Q71/verilog/multl6s/multl6s.bdf" { { 232 8 176 248 "A\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.058 ns) + CELL(4.712 ns) 12.765 ns lpm_mult0:inst2\|lpm_mult:lpm_mult_component\|mult_6bn:auto_generated\|mac_mult1~DATAOUT18 2 COMB DSPMULT_X16_Y10_N0 1 " "Info: 2: + IC(7.058 ns) + CELL(4.712 ns) = 12.765 ns; Loc. = DSPMULT_X16_Y10_N0; Fanout = 1; COMB Node = 'lpm_mult0:inst2\|lpm_mult:lpm_mult_component\|mult_6bn:auto_generated\|mac_mult1~DATAOUT18'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.770 ns" { A[12] lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT18 } "NODE_NAME" } } { "db/mult_6bn.tdf" "" { Text "G:/Q71/verilog/multl6s/db/mult_6bn.tdf" 35 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.396 ns) 13.161 ns lpm_mult0:inst2\|lpm_mult:lpm_mult_component\|mult_6bn:auto_generated\|result\[18\] 3 COMB DSPOUT_X16_Y10_N2 1 " "Info: 3: + IC(0.000 ns) + CELL(0.396 ns) = 13.161 ns; Loc. = DSPOUT_X16_Y10_N2; Fanout = 1; COMB Node = 'lpm_mult0:inst2\|lpm_mult:lpm_mult_component\|mult_6bn:auto_generated\|result\[18\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.396 ns" { lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT18 lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|result[18] } "NODE_NAME" } } { "db/mult_6bn.tdf" "" { Text "G:/Q71/verilog/multl6s/db/mult_6bn.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(3.286 ns) 19.166 ns P\[18\] 4 PIN PIN_201 0 " "Info: 4: + IC(2.719 ns) + CELL(3.286 ns) = 19.166 ns; Loc. = PIN_201; Fanout = 0; PIN Node = 'P\[18\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.005 ns" { lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|result[18] P[18] } "NODE_NAME" } } { "multl6s.bdf" "" { Schematic "G:/Q71/verilog/multl6s/multl6s.bdf" { { 248 400 576 264 "P\[31..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.389 ns ( 48.99 % ) " "Info: Total cell delay = 9.389 ns ( 48.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.777 ns ( 51.01 % ) " "Info: Total interconnect delay = 9.777 ns ( 51.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "19.166 ns" { A[12] lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT18 lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|result[18] P[18] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "19.166 ns" { A[12] {} A[12]~combout {} lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT18 {} lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|result[18] {} P[18] {} } { 0.000ns 0.000ns 7.058ns 0.000ns 2.719ns } { 0.000ns 0.995ns 4.712ns 0.396ns 3.286ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 15 13:49:41 2007 " "Info: Processing ended: Sat Dec 15 13:49:41 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}