multl6s.map.qmsg

Verilog 经典实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 15 13:49:29 2007 " "Info: Processing started: Sat Dec 15 13:49:29 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off multl6s -c multl6s " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off multl6s -c multl6s" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "P p mult16S.v(6) " "Info (10281): Verilog HDL Declaration information at mult16S.v(6): object \"P\" differs only in case from object \"p\" in the same scope" {  } { { "mult16S.v" "" { Text "G:/Q71/verilog/multl6s/mult16S.v" 6 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "A a mult16S.v(8) " "Info (10281): Verilog HDL Declaration information at mult16S.v(8): object \"A\" differs only in case from object \"a\" in the same scope" {  } { { "mult16S.v" "" { Text "G:/Q71/verilog/multl6s/mult16S.v" 8 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "B b mult16S.v(9) " "Info (10281): Verilog HDL Declaration information at mult16S.v(9): object \"B\" differs only in case from object \"b\" in the same scope" {  } { { "mult16S.v" "" { Text "G:/Q71/verilog/multl6s/mult16S.v" 9 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult16S.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mult16S.v" { { "Info" "ISGN_ENTITY_NAME" "1 mult16S " "Info: Found entity 1: mult16S" {  } { { "mult16S.v" "" { Text "G:/Q71/verilog/multl6s/mult16S.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "multl6s.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file multl6s.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 multl6s " "Info: Found entity 1: multl6s" {  } { { "multl6s.bdf" "" { Schematic "G:/Q71/verilog/multl6s/multl6s.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "multl6s " "Info: Elaborating entity \"multl6s\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_mult0.v 1 1 " "Warning: Using design file lpm_mult0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult0 " "Info: Found entity 1: lpm_mult0" {  } { { "lpm_mult0.v" "" { Text "G:/Q71/verilog/multl6s/lpm_mult0.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult0 lpm_mult0:inst2 " "Info: Elaborating entity \"lpm_mult0\" for hierarchy \"lpm_mult0:inst2\"" {  } { { "multl6s.bdf" "inst2" { Schematic "G:/Q71/verilog/multl6s/multl6s.bdf" { { 200 208 376 296 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/72/quartus/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "g:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf" 284 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult lpm_mult0:inst2\|lpm_mult:lpm_mult_component " "Info: Elaborating entity \"lpm_mult\" for hierarchy \"lpm_mult0:inst2\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult0.v" "lpm_mult_component" { Text "G:/Q71/verilog/multl6s/lpm_mult0.v" 58 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult0:inst2\|lpm_mult:lpm_mult_component " "Info: Elaborated megafunction instantiation \"lpm_mult0:inst2\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult0.v" "" { Text "G:/Q71/verilog/multl6s/lpm_mult0.v" 58 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_6bn.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_6bn.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_6bn " "Info: Found entity 1: mult_6bn" {  } { { "db/mult_6bn.tdf" "" { Text "G:/Q71/verilog/multl6s/db/mult_6bn.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_6bn lpm_mult0:inst2\|lpm_mult:lpm_mult_component\|mult_6bn:auto_generated " "Info: Elaborating entity \"mult_6bn\" for hierarchy \"lpm_mult0:inst2\|lpm_mult:lpm_mult_component\|mult_6bn:auto_generated\"" {  } { { "lpm_mult.tdf" "auto_generated" { Text "g:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "G:/Q71/verilog/multl6s/multl6s.map.smsg " "Info: Generated suppressed messages file G:/Q71/verilog/multl6s/multl6s.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "67 " "Info: Implemented 67 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "32 " "Info: Implemented 32 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Info: Implemented 1 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_DSP_ELEM" "2 " "Info: Implemented 2 DSP elements" {  } {  } 0 0 "Implemented %1!d! DSP elements" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 15 13:49:31 2007 " "Info: Processing ended: Sat Dec 15 13:49:31 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}