mult_6bn.tdf

Verilog 经典实例

--lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" DSP_BLOCK_BALANCING="Auto" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTHA=16 LPM_WIDTHB=16 LPM_WIDTHP=32 MAXIMIZE_SPEED=5 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 7.2 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_mult 2007:07:20:16:47:26:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_padd 2007:07:12:14:48:24:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END


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FUNCTION cycloneii_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb)
WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock)
RETURNS ( dataout[dataa_width+datab_width-1..0]);
FUNCTION cycloneii_mac_out (aclr, clk, dataa[dataa_width-1..0], ena)
WITH ( dataa_width = 0, output_clock)
RETURNS ( dataout[dataa_width-1..0]);

--synthesis_resources = dsp_9bit 2 
SUBDESIGN mult_6bn
( 
	dataa[15..0]	:	input;
	datab[15..0]	:	input;
	result[31..0]	:	output;
) 
VARIABLE 
	mac_mult1 : cycloneii_mac_mult
		WITH (
			dataa_clock = "none",
			dataa_width = 16,
			datab_clock = "none",
			datab_width = 16,
			signa_clock = "none",
			signb_clock = "none"
		);
	mac_out2 : cycloneii_mac_out
		WITH (
			dataa_width = 32,
			output_clock = "none"
		);

BEGIN 
	mac_mult1.dataa[] = ( dataa[]);
	mac_mult1.datab[] = ( datab[]);
	mac_mult1.signa = B"0";
	mac_mult1.signb = B"0";
	mac_out2.dataa[] = mac_mult1.dataout[];
	result[31..0] = mac_out2.dataout[31..0];
END;
--VALID FILE