mult16s.v.bak

来自「Verilog 经典实例」· BAK 代码 · 共 44 行

// ------------------------------------------------------------------------
//16-bit multiplier
//Filename : mult16S.v : P = A * B 
//-------------------------------------------------------------------------
module mult16S(P,A,B);
output [31:0]P;	// 32-bit product
						
input [15:0]A;	//Multiplicand 	
input [15:0]B;	//Multiplier	

reg [31:0] p;

reg [15:0] a;
reg [15:0] b;


always @(A or B)
   begin
reg [31:0] temp;
reg [15:0] bitN;
	a = A;
	b = B;
	if (a==0 || b==0) 	// q=0 when a or b equal 0			
		p = 31'b0;        
	else if (a==1)		// q=b when a equal 1
		p = b;
	else if (b==1)		// q=a when b equal 1
		p = a;
	else 
		begin
		p = 31'b0;
		for (bitN=0; bitN<16; bitN = bitN + 1)	
			if  (b[bitN] == 1'b1)
				begin
                     temp = a << bitN;	// shift left N bits				
                     p = p + temp; 
				end
		end
    end
assign P = p;


endmodule