multl6s.map.rpt
来自「Verilog 经典实例」· RPT 代码 · 共 319 行 · 第 1/2 页
RPT
319 行
; -- normal mode ; 1 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 64 ;
; Embedded Multiplier 9-bit elements ; 2 ;
; Maximum fan-out node ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|result[0] ;
; Maximum fan-out ; 32 ;
; Total fan-out ; 66 ;
; Average fan-out ; 0.99 ;
+---------------------------------------------+-------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+-------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------+--------------+
; |multl6s ; 1 (1) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 64 ; 0 ; |multl6s ; work ;
; |lpm_mult0:inst2| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |multl6s|lpm_mult0:inst2 ; work ;
; |lpm_mult:lpm_mult_component| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component ; work ;
; |mult_6bn:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated ; work ;
+-------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary ;
+---------------------------------------+-------------+
; Statistic ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit) ; 0 ;
; Simple Multipliers (18-bit) ; 1 ;
; Embedded Multiplier Blocks ; -- ;
; Embedded Multiplier 9-bit elements ; 2 ;
; Signed Embedded Multipliers ; 0 ;
; Unsigned Embedded Multipliers ; 1 ;
; Mixed Sign Embedded Multipliers ; 0 ;
; Variable Sign Embedded Multipliers ; 0 ;
; Dedicated Input Shift Register Chains ; 0 ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_mult0:inst2|lpm_mult:lpm_mult_component ;
+------------------------------------------------+------------+----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------------------+------------+----------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTHA ; 16 ; Signed Integer ;
; LPM_WIDTHB ; 16 ; Signed Integer ;
; LPM_WIDTHP ; 32 ; Signed Integer ;
; LPM_WIDTHR ; 0 ; Untyped ;
; LPM_WIDTHS ; 1 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; LATENCY ; 0 ; Untyped ;
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
; USE_EAB ; OFF ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; CBXI_PARAMETER ; mult_6bn ; Untyped ;
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
+------------------------------------------------+------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance ;
+---------------------------------------+---------------------------------------------+
; Name ; Value ;
+---------------------------------------+---------------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; lpm_mult0:inst2|lpm_mult:lpm_mult_component ;
; -- LPM_WIDTHA ; 16 ;
; -- LPM_WIDTHB ; 16 ;
; -- LPM_WIDTHP ; 32 ;
; -- LPM_REPRESENTATION ; UNSIGNED ;
; -- INPUT_A_IS_CONSTANT ; NO ;
; -- INPUT_B_IS_CONSTANT ; NO ;
; -- USE_EAB ; OFF ;
; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ;
; -- INPUT_A_FIXED_VALUE ; Bx ;
; -- INPUT_B_FIXED_VALUE ; Bx ;
+---------------------------------------+---------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Sat Dec 15 13:49:29 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off multl6s -c multl6s
Info: Found 1 design units, including 1 entities, in source file mult16S.v
Info: Found entity 1: mult16S
Info: Found 1 design units, including 1 entities, in source file multl6s.bdf
Info: Found entity 1: multl6s
Info: Elaborating entity "multl6s" for the top level hierarchy
Warning: Using design file lpm_mult0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: lpm_mult0
Info: Elaborating entity "lpm_mult0" for hierarchy "lpm_mult0:inst2"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/lpm_mult.tdf
Info: Found entity 1: lpm_mult
Info: Elaborating entity "lpm_mult" for hierarchy "lpm_mult0:inst2|lpm_mult:lpm_mult_component"
Info: Elaborated megafunction instantiation "lpm_mult0:inst2|lpm_mult:lpm_mult_component"
Info: Found 1 design units, including 1 entities, in source file db/mult_6bn.tdf
Info: Found entity 1: mult_6bn
Info: Elaborating entity "mult_6bn" for hierarchy "lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated"
Info: Generated suppressed messages file G:/Q71/verilog/multl6s/multl6s.map.smsg
Info: Implemented 67 device resources after synthesis - the final resource count might be different
Info: Implemented 32 input pins
Info: Implemented 32 output pins
Info: Implemented 1 logic cells
Info: Implemented 2 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 140 megabytes of memory during processing
Info: Processing ended: Sat Dec 15 13:49:31 2007
Info: Elapsed time: 00:00:02
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in G:/Q71/verilog/multl6s/multl6s.map.smsg.
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