multl6s.fit.summary

来自「Verilog 经典实例」· SUMMARY 代码 · 共 17 行

Fitter Status : Successful - Sat Dec 15 13:49:36 2007
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : multl6s
Top-level Entity Name : multl6s
Family : Cyclone II
Device : EP2C5Q208C8
Timing Models : Final
Total logic elements : 1 / 4,608 ( < 1 % )
    Total combinational functions : 1 / 4,608 ( < 1 % )
    Dedicated logic registers : 0 / 4,608 ( 0 % )
Total registers : 0
Total pins : 64 / 142 ( 45 % )
Total virtual pins : 0
Total memory bits : 0 / 119,808 ( 0 % )
Embedded Multiplier 9-bit elements : 2 / 26 ( 8 % )
Total PLLs : 0 / 2 ( 0 % )