multl6s.sim.rpt
来自「Verilog 经典实例」· RPT 代码 · 共 371 行 · 第 1/4 页
RPT
371 行
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~2 ; dataout2 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~3 ; dataout3 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT13 ; dataout17 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT14 ; dataout18 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT15 ; dataout19 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT16 ; dataout20 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT17 ; dataout21 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT18 ; dataout22 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT19 ; dataout23 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT20 ; dataout24 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT21 ; dataout25 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT22 ; dataout26 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT23 ; dataout27 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT24 ; dataout28 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT25 ; dataout29 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT26 ; dataout30 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT27 ; dataout31 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT28 ; dataout32 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT29 ; dataout33 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT30 ; dataout34 ;
; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1 ; |multl6s|lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_6bn:auto_generated|mac_mult1~DATAOUT31 ; dataout35 ;
; |multl6s|~GND ; |multl6s|~GND ; combout ;
; |multl6s|P[31] ; |multl6s|P[31] ; padio ;
; |multl6s|P[30] ; |multl6s|P[30] ; padio ;
; |multl6s|P[29] ; |multl6s|P[29] ; padio ;
; |multl6s|P[28] ; |multl6s|P[28] ; padio ;
; |multl6s|P[27] ; |multl6s|P[27] ; padio ;
; |multl6s|P[26] ; |multl6s|P[26] ; padio ;
; |multl6s|P[25] ; |multl6s|P[25] ; padio ;
; |multl6s|P[24] ; |multl6s|P[24] ; padio ;
; |multl6s|P[23] ; |multl6s|P[23] ; padio ;
; |multl6s|P[22] ; |multl6s|P[22] ; padio ;
; |multl6s|P[21] ; |multl6s|P[21] ; padio ;
; |multl6s|P[20] ; |multl6s|P[20] ; padio ;
; |multl6s|P[19] ; |multl6s|P[19] ; padio ;
; |multl6s|P[18] ; |multl6s|P[18] ; padio ;
; |multl6s|P[17] ; |multl6s|P[17] ; padio ;
; |multl6s|P[16] ; |multl6s|P[16] ; padio ;
; |multl6s|P[15] ; |multl6s|P[15] ; padio ;
; |multl6s|P[14] ; |multl6s|P[14] ; padio ;
; |multl6s|P[13] ; |multl6s|P[13] ; padio ;
; |multl6s|A[6] ; |multl6s|A[6]~corein ; combout ;
; |multl6s|A[7] ; |multl6s|A[7]~corein ; combout ;
; |multl6s|A[8] ; |multl6s|A[8]~corein ; combout ;
; |multl6s|A[9] ; |multl6s|A[9]~corein ; combout ;
; |multl6s|A[10] ; |multl6s|A[10]~corein ; combout ;
; |multl6s|A[11] ; |multl6s|A[11]~corein ; combout ;
; |multl6s|A[12] ; |multl6s|A[12]~corein ; combout ;
; |multl6s|A[13] ; |multl6s|A[13]~corein ; combout ;
; |multl6s|A[14] ; |multl6s|A[14]~corein ; combout ;
; |multl6s|A[15] ; |multl6s|A[15]~corein ; combout ;
; |multl6s|B[6] ; |multl6s|B[6]~corein ; combout ;
; |multl6s|B[7] ; |multl6s|B[7]~corein ; combout ;
; |multl6s|B[8] ; |multl6s|B[8]~corein ; combout ;
; |multl6s|B[9] ; |multl6s|B[9]~corein ; combout ;
; |multl6s|B[10] ; |multl6s|B[10]~corein ; combout ;
; |multl6s|B[11] ; |multl6s|B[11]~corein ; combout ;
; |multl6s|B[12] ; |multl6s|B[12]~corein ; combout ;
; |multl6s|B[13] ; |multl6s|B[13]~corein ; combout ;
; |multl6s|B[14] ; |multl6s|B[14]~corein ; combout ;
; |multl6s|B[15] ; |multl6s|B[15]~corein ; combout ;
+----------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Sat Dec 15 13:52:09 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off multl6s -c multl6s
Info: Using vector source file "G:/Q71/verilog/multl6s/multl6s.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 38.35 %
Info: Number of transitions in simulation is 2561
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 102 megabytes of memory during processing
Info: Processing ended: Sat Dec 15 13:52:11 2007
Info: Elapsed time: 00:00:02
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