multl6s.map.summary

来自「Verilog 经典实例」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Sat Dec 15 13:49:31 2007
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : multl6s
Top-level Entity Name : multl6s
Family : Cyclone II
Total logic elements : 1
    Total combinational functions : 1
    Dedicated logic registers : 0
Total registers : 0
Total pins : 64
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 2
Total PLLs : 0