tt.map.summary

来自「Verilog 经典实例」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Fri Jan 11 02:18:31 2008
Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Full Version
Revision Name : tt
Top-level Entity Name : tt
Family : Cyclone
Total logic elements : 608
Total pins : 21
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0