tt.tan.summary

Verilog 经典实例

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.206 ns
From           : ad_data
To             : ADC_TLC549:inst|data_reg[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 24.298 ns
From           : bin27seg:inst1|datain[0][0]
To             : 78leddata[5]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.154 ns
From           : ad_data
To             : ADC_TLC549:inst|data_reg[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 15.41 MHz ( period = 64.878 ns )
From           : ADC_TLC549:inst|data_temp[4]
To             : bin27seg:inst1|datain[1][3]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : ADC_TLC549:inst|data_temp[6]
To             : bin27seg:inst1|datain[0][0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 25

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 25

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