adc_tlc549.v.bak

Verilog 经典实例

`timescale 1ns / 1ps
// synthesis translate_on
module ADC_TLC549 (
                   // inputs:
                    clk,
                    read_n,
                   // outputs:
                    AD_DATA,
                    AD_CS,
                    AD_CLK,
                    irq,
                    readdata                     
                 )
;

  input           AD_DATA;
  output           AD_CS;
  output           AD_CLK;
  output           irq;
  output   [7: 0]  readdata;
  input            read_n;
  input            clk;
  wire             AD_DATA;
  reg              AD_CLK_r;
  reg     [10:0]   DCLK_DIV;
  reg     [4:0]    COUNTER;
  reg     [7:0]   data_temp;
  reg     [7:0]   data_reg;

  wire    [7: 0] readdata;
  wire            AD_CS;

parameter CLK_FREQ = 'D50_000_000;//系统时钟50MHZ
parameter DCLK_FREQ = 'D1_000_000;//AD_CLK输出时钟1MHZ

assign readdata = read_n ? 8'h00 : data_temp;

always @(posedge clk)
  if(DCLK_DIV < (CLK_FREQ / DCLK_FREQ))
    DCLK_DIV <= DCLK_DIV+1'b1;
  else
    begin 
      DCLK_DIV <= 0;
      AD_CLK_r <= ~AD_CLK_r;
    end


always @(posedge AD_CLK_r)
      COUNTER <= COUNTER+1'b1;

assign AD_CS = COUNTER <= 'd9 ? 1'b0 : 1'b1;
assign AD_CLK =  AD_CLK_EN ? AD_CLK_r : 1'b1;
assign AD_CLK_EN = (COUNTER >= 'd2 && COUNTER <= 'd9) ? 1'b1 : 1'b0;
assign irq =  (COUNTER == 'd10) ? 1'b1 : 1'b0;


always @(negedge AD_CLK_r)
 if(AD_CLK_EN) 
     begin
       data_reg[0] <= AD_DATA;
       data_reg[7:1] <= data_reg[6:0];//串并转换
     end
  else
    data_temp <= data_reg ;


  //control_slave, which is an e_avalon_slave

endmodule