i2c_test.v

来自「Verilog 经典实例」· Verilog 代码 · 共 25 行

module i2c_test(clk,rst,data_out,wr_input,rd_input,wr_output,rd_output);

input clk,rst,wr_input,rd_input;
output[3:0] data_out;//输入写入EEPROM的数据
output wr_output;//要求写的输入
output rd_output;//要求读的输入

reg  [3:0]counter;


assign data_out=counter;
assign wr_output=wr_input;
assign rd_output=rd_input;

always @(negedge wr_input or negedge rst )
 begin
   if(!rst)
      counter<=0;
   else if(counter<=8'hff)
      counter<=counter+1'b1;
   else
      counter<=0;
  end

endmodule