i2c_fpga.map.qmsg

Verilog 经典实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 20 15:37:22 2006 " "Info: Processing started: Mon Nov 20 15:37:22 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off I2C_FPGA -c I2C_FPGA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off I2C_FPGA -c I2C_FPGA" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I2C_FPGA.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file I2C_FPGA.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_FPGA " "Info: Found entity 1: I2C_FPGA" {  } { { "I2C_FPGA.bdf" "" { Schematic "D:/I2C_CPLD/I2C_FPGA.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c " "Info: Found entity 1: i2c" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 13 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c_test.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_test " "Info: Found entity 1: i2c_test" {  } { { "i2c_test.v" "" { Text "D:/I2C_CPLD/i2c_test.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "I2C_FPGA " "Info: Elaborating entity \"I2C_FPGA\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c i2c:inst4 " "Info: Elaborating entity \"i2c\" for hierarchy \"i2c:inst4\"" {  } { { "I2C_FPGA.bdf" "inst4" { Schematic "D:/I2C_CPLD/I2C_FPGA.bdf" { { -40 624 808 88 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 i2c.v(78) " "Warning (10230): Verilog HDL assignment warning at i2c.v(78): truncated value with size 32 to match size of target (20)" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 78 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c.v(96) " "Warning (10230): Verilog HDL assignment warning at i2c.v(96): truncated value with size 32 to match size of target (8)" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 96 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(161) " "Warning (10270): Verilog HDL statement warning at i2c.v(161): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 161 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(161) " "Info (10264): Verilog HDL Case Statement information at i2c.v(161): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 161 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(237) " "Warning (10270): Verilog HDL statement warning at i2c.v(237): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 237 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(237) " "Info (10264): Verilog HDL Case Statement information at i2c.v(237): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 237 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(302) " "Warning (10270): Verilog HDL statement warning at i2c.v(302): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 302 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(302) " "Info (10264): Verilog HDL Case Statement information at i2c.v(302): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 302 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(159) " "Info (10264): Verilog HDL Case Statement information at i2c.v(159): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 159 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(383) " "Warning (10270): Verilog HDL statement warning at i2c.v(383): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 383 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(383) " "Info (10264): Verilog HDL Case Statement information at i2c.v(383): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 383 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(459) " "Warning (10270): Verilog HDL statement warning at i2c.v(459): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 459 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(459) " "Info (10264): Verilog HDL Case Statement information at i2c.v(459): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 459 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(524) " "Warning (10270): Verilog HDL statement warning at i2c.v(524): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 524 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(524) " "Info (10264): Verilog HDL Case Statement information at i2c.v(524): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 524 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(599) " "Warning (10270): Verilog HDL statement warning at i2c.v(599): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 599 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(599) " "Info (10264): Verilog HDL Case Statement information at i2c.v(599): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 599 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}