beep.map.summary

来自「Verilog 经典实例」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Mon Nov 20 21:22:01 2006
Quartus II Version : 5.1 Build 216 03/06/2006 SP 2 SJ Full Version
Revision Name : beep
Top-level Entity Name : beep
Family : MAX II
Total logic elements : 104
Total pins : 3
Total virtual pins : 0
UFM blocks : 0