da_tlc5620.fit.rpt

Verilog 经典实例

; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in G:/Q71/verilog/DA_TLC5620/DA_TLC5620.pin.


+----------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                  ;
+---------------------------------------------+------------------------------------------------------------------+
; Resource                                    ; Usage                                                            ;
+---------------------------------------------+------------------------------------------------------------------+
; Total logic elements                        ; 825 / 4,608 ( 18 % )                                             ;
;     -- Combinational with no register       ; 680                                                              ;
;     -- Register only                        ; 0                                                                ;
;     -- Combinational with a register        ; 145                                                              ;
;                                             ;                                                                  ;
; Logic element usage by number of LUT inputs ;                                                                  ;
;     -- 4 input functions                    ; 161                                                              ;
;     -- 3 input functions                    ; 190                                                              ;
;     -- <=2 input functions                  ; 474                                                              ;
;     -- Register only                        ; 0                                                                ;
;                                             ;                                                                  ;
; Logic elements by mode                      ;                                                                  ;
;     -- normal mode                          ; 523                                                              ;
;     -- arithmetic mode                      ; 302                                                              ;
;                                             ;                                                                  ;
; Total registers*                            ; 145 / 5,010 ( 3 % )                                              ;
;     -- Dedicated logic registers            ; 145 / 4,608 ( 3 % )                                              ;
;     -- I/O registers                        ; 0 / 402 ( 0 % )                                                  ;
;                                             ;                                                                  ;
; Total LABs:  partially or completely used   ; 63 / 288 ( 22 % )                                                ;
; User inserted logic elements                ; 0                                                                ;
; Virtual pins                                ; 0                                                                ;
; I/O pins                                    ; 26 / 142 ( 18 % )                                                ;
;     -- Clock pins                           ; 1 / 4 ( 25 % )                                                   ;
; Global signals                              ; 3                                                                ;
; M4Ks                                        ; 0 / 26 ( 0 % )                                                   ;
; Total memory bits                           ; 0 / 119,808 ( 0 % )                                              ;
; Total RAM block bits                        ; 0 / 119,808 ( 0 % )                                              ;
; Embedded Multiplier 9-bit elements          ; 2 / 26 ( 8 % )                                                   ;
; PLLs                                        ; 0 / 2 ( 0 % )                                                    ;
; Global clocks                               ; 3 / 8 ( 38 % )                                                   ;
; Average interconnect usage                  ; 3%                                                               ;
; Peak interconnect usage                     ; 5%                                                               ;
; Maximum fan-out node                        ; dac_test:inst1|lpm_mult:Mult0|mult_9111:auto_generated|result[0] ;
; Maximum fan-out                             ; 153                                                              ;
; Highest non-global fan-out signal           ; reset                                                            ;
; Highest non-global fan-out                  ; 63                                                               ;
; Total fan-out                               ; 2548                                                             ;
; Average fan-out                             ; 2.54                                                             ;
+---------------------------------------------+------------------------------------------------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                   ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk    ; 23    ; 1        ; 0            ; 6            ; 0           ; 3                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;