da_tlc5620.tan.summary

来自「Verilog 经典实例」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.486 ns
From           : key[1]
To             : dac_test:inst1|data_code_r[7]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 18.656 ns
From           : dac_test:inst1|datain[0][1]
To             : 78leddata[3]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.482 ns
From           : key[2]
To             : dac_test:inst1|key2_r[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 11.26 MHz ( period = 88.790 ns )
From           : dac_test:inst1|data_code_r[0]
To             : dac_test:inst1|datain[1][1]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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