lcd_1602.hier_info

Verilog 经典实例

|lcd_1602
lcd_e <= lcd:inst.lcd_e
clk => lcd:inst.clk
reset => lcd:inst.rst
lcd_rs <= lcd:inst.lcd_rs
lcd_rw <= lcd:inst.lcd_rw
lcd_data[0] <= lcd:inst.data[0]
lcd_data[1] <= lcd:inst.data[1]
lcd_data[2] <= lcd:inst.data[2]
lcd_data[3] <= lcd:inst.data[3]
lcd_data[4] <= lcd:inst.data[4]
lcd_data[5] <= lcd:inst.data[5]
lcd_data[6] <= lcd:inst.data[6]
lcd_data[7] <= lcd:inst.data[7]


|lcd_1602|lcd:inst
clk => clkcnt[19].CLK
clk => clkcnt[18].CLK
clk => clkcnt[17].CLK
clk => clkcnt[16].CLK
clk => clkcnt[15].CLK
clk => clkcnt[14].CLK
clk => clkcnt[13].CLK
clk => clkcnt[12].CLK
clk => clkcnt[11].CLK
clk => clkcnt[10].CLK
clk => clkcnt[9].CLK
clk => clkcnt[8].CLK
clk => clkcnt[7].CLK
clk => clkcnt[6].CLK
clk => clkcnt[5].CLK
clk => clkcnt[4].CLK
clk => clkcnt[3].CLK
clk => clkcnt[2].CLK
clk => clkcnt[1].CLK
clk => clkcnt[0].CLK
clk => clkcnt[20].CLK
rst => clkdiv~0.OUTPUTSELECT
rst => clk_int~0.OUTPUTSELECT
rst => lcd_e~0.OUTPUTSELECT
rst => flag.ACLR
rst => counter[6].ACLR
rst => counter[5].ACLR
rst => counter[4].ACLR
rst => counter[3].ACLR
rst => counter[2].ACLR
rst => counter[1].ACLR
rst => counter[0].ACLR
rst => divcounter[3].ACLR
rst => divcounter[2].ACLR
rst => divcounter[1].ACLR
rst => divcounter[0].ACLR
rst => address[5].ACLR
rst => address[4].ACLR
rst => address[3].ACLR
rst => address[2].ACLR
rst => address[1].ACLR
rst => address[0].ACLR
rst => clkcnt~21.OUTPUTSELECT
rst => clkcnt~22.OUTPUTSELECT
rst => clkcnt~23.OUTPUTSELECT
rst => clkcnt~24.OUTPUTSELECT
rst => clkcnt~25.OUTPUTSELECT
rst => clkcnt~26.OUTPUTSELECT
rst => clkcnt~27.OUTPUTSELECT
rst => clkcnt~28.OUTPUTSELECT
rst => clkcnt~29.OUTPUTSELECT
rst => clkcnt~30.OUTPUTSELECT
rst => clkcnt~31.OUTPUTSELECT
rst => clkcnt~32.OUTPUTSELECT
rst => clkcnt~33.OUTPUTSELECT
rst => clkcnt~34.OUTPUTSELECT
rst => clkcnt~35.OUTPUTSELECT
rst => clkcnt~36.OUTPUTSELECT
rst => clkcnt~37.OUTPUTSELECT
rst => clkcnt~38.OUTPUTSELECT
rst => clkcnt~39.OUTPUTSELECT
rst => clkcnt~40.OUTPUTSELECT
rst => clkcnt~41.OUTPUTSELECT
rst => lcd_rw~reg0.ENA
rst => lcd_rs~reg0.ENA
rst => data[7]~reg0.ENA
rst => data[6]~reg0.ENA
rst => data[5]~reg0.ENA
rst => data[4]~reg0.ENA
rst => data[3]~reg0.ENA
rst => data[2]~reg0.ENA
rst => data[1]~reg0.ENA
rst => data[0]~reg0.ENA
rst => state~12.IN1
lcd_e <= lcd_e~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rw <= lcd_rw~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rs <= lcd_rs~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|lcd_1602|lcd:inst|char_ram:charram
address[0] => Mux~0.IN69
address[0] => Mux~1.IN69
address[0] => Mux~2.IN69
address[0] => Mux~3.IN69
address[0] => Mux~4.IN69
address[0] => Mux~5.IN69
address[0] => Mux~6.IN69
address[1] => Mux~0.IN68
address[1] => Mux~1.IN68
address[1] => Mux~2.IN68
address[1] => Mux~3.IN68
address[1] => Mux~4.IN68
address[1] => Mux~5.IN68
address[1] => Mux~6.IN68
address[2] => Mux~0.IN67
address[2] => Mux~1.IN67
address[2] => Mux~2.IN67
address[2] => Mux~3.IN67
address[2] => Mux~4.IN67
address[2] => Mux~5.IN67
address[2] => Mux~6.IN67
address[3] => Mux~0.IN66
address[3] => Mux~1.IN66
address[3] => Mux~2.IN66
address[3] => Mux~3.IN66
address[3] => Mux~4.IN66
address[3] => Mux~5.IN66
address[3] => Mux~6.IN66
address[4] => Mux~0.IN65
address[4] => Mux~1.IN65
address[4] => Mux~2.IN65
address[4] => Mux~3.IN65
address[4] => Mux~4.IN65
address[4] => Mux~5.IN65
address[4] => Mux~6.IN65
address[5] => Mux~0.IN64
address[5] => Mux~1.IN64
address[5] => Mux~2.IN64
address[5] => Mux~3.IN64
address[5] => Mux~4.IN64
address[5] => Mux~5.IN64
address[5] => Mux~6.IN64
data[0] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= <GND>