segmain.v

来自「Verilog 经典实例」· Verilog 代码 · 共 52 行

module segmain
  ( 
	clk,
	rst,
	datain,
	dataout,
	ledcom
   );
    input  		 clk;
	input  		 rst;
	input [15:0] datain;
	output [3:0] dataout;
	output [3:0] ledcom;
	
	reg [3:0]    ledcom;
	reg [1:0]	 comclk;
	reg [3:0]	 bcd_led;
	
	always @(posedge clk or posedge rst)
	begin
	   if (rst) begin
	      comclk <= 0;
	   end
	   else begin
	      if (comclk >= 2'b11) begin
	          comclk <= 0;
	      end
	      else begin
	          comclk <= comclk + 1;
	      end
	   end
	end
	
	always @ (comclk)
	begin
		if (comclk == 2'b00) ledcom <= 4'b0001;
		else if (comclk == 2'b01) ledcom <= 4'b0010;
		else if (comclk == 2'b10) ledcom <= 4'b0100;
		else ledcom <= 4'b1000;
	end
	
	always @ (comclk)
	begin
		if (comclk == 2'b00) bcd_led <= datain[3:0];
		else if (comclk == 2'b01) bcd_led <= datain[7:4];
		else if (comclk == 2'b10) bcd_led <= datain[11:8];
		else bcd_led <= datain[15:12];
	end
	
	assign dataout = bcd_led;
endmodule