📄 ps2.map.rpt
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+------------------------+---------+----------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+---------+----------------------------------------------------------------------+
; LPM_WIDTH ; 1 ; Integer ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_FFTYPE ; DFF ; Untyped ;
; DEVICE_FAMILY ; MAX II ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+---------+----------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component ;
+------------------------+---------+----------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+---------+----------------------------------------------------------------------+
; LPM_WIDTH ; 1 ; Integer ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_FFTYPE ; DFF ; Untyped ;
; DEVICE_FAMILY ; MAX II ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+---------+----------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: convert:inst1|mydff:dff_component3|lpm_ff:lpm_ff_component ;
+------------------------+---------+----------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+---------+----------------------------------------------------------------------+
; LPM_WIDTH ; 1 ; Integer ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_FFTYPE ; DFF ; Untyped ;
; DEVICE_FAMILY ; MAX II ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+---------+----------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/Verilog_PS2_1c12/PS2.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
Info: Processing started: Sun Nov 19 23:02:19 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PS2 -c PS2
Info: Found 1 design units, including 1 entities, in source file PS2.bdf
Info: Found entity 1: PS2
Warning (10268): Verilog HDL information at data_scanC.v(25): Always Construct contains both blocking and non-blocking assignments
Info: Found 1 design units, including 1 entities, in source file data_scanC.v
Info: Found entity 1: data_scanC
Info: Found 1 design units, including 1 entities, in source file convert.v
Info: Found entity 1: convert
Info: Found 1 design units, including 1 entities, in source file mydff.v
Info: Found entity 1: mydff
Info: Found 1 design units, including 1 entities, in source file segmain.v
Info: Found entity 1: segmain
Info: Found 1 design units, including 1 entities, in source file bin27seg.v
Info: Found entity 1: bin27seg
Info: Elaborating entity "PS2" for the top level hierarchy
Warning: Found inconsistent dimensions
Warning: Port "ZHJS" of type data_scanC and instance "inst" is missing source signal
Warning: Port "PA" of type data_scanC and instance "inst" is missing source signal
Info: Elaborating entity "segmain" for hierarchy "segmain:inst9"
Warning (10230): Verilog HDL assignment warning at segmain.v(29): truncated value with size 32 to match size of target (2)
Warning (10235): Verilog HDL Always Construct warning at segmain.v(44): variable "datain" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at segmain.v(45): variable "datain" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at segmain.v(46): variable "datain" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at segmain.v(47): variable "datain" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Using design file lpm_counter0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: lpm_counter0-SYN
Info: Found entity 1: lpm_counter0
Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst5"
Info: Found 1 design units, including 1 entities, in source file ../altera/quartus51/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst5|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_69d.tdf
Info: Found entity 1: cntr_69d
Info: Elaborating entity "cntr_69d" for hierarchy "lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated"
Info: Elaborating entity "data_scanC" for hierarchy "data_scanC:inst"
Warning (10230): Verilog HDL assignment warning at data_scanC.v(46): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "convert" for hierarchy "convert:inst1"
Warning (10235): Verilog HDL Always Construct warning at convert.v(37): variable "shifted" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at convert.v(44): variable "capslocked" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10270): Verilog HDL statement warning at convert.v(59): incomplete Case Statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at convert.v(53): variable "tmpASCII" may not be assigned a new value in every possible path through the Always Construct. Variable "tmpASCII" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "mydff" for hierarchy "convert:inst1|mydff:dff_component1"
Info: Found 1 design units, including 1 entities, in source file ../altera/quartus51/libraries/megafunctions/lpm_ff.tdf
Info: Found entity 1: lpm_ff
Info: Elaborating entity "lpm_ff" for hierarchy "convert:inst1|mydff:dff_component1|lpm_ff:lpm_ff_component"
Info: Elaborating entity "bin27seg" for hierarchy "bin27seg:inst3"
Warning: Latch convert:inst1|tmpASCII[0] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst|started
Warning: Latch convert:inst1|tmpASCII[4] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst|started
Warning: Latch convert:inst1|tmpASCII[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst|started
Warning: Latch convert:inst1|tmpASCII[5] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst|started
Warning: Latch convert:inst1|tmpASCII[6] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst|started
Warning: Latch convert:inst1|tmpASCII[3] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst|started
Warning: Latch convert:inst1|tmpASCII[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal data_scanC:inst|started
Info: Implemented 245 device resources after synthesis - the final resource count might be different
Info: Implemented 4 input pins
Info: Implemented 11 output pins
Info: Implemented 230 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 29 warnings
Info: Processing ended: Sun Nov 19 23:02:46 2006
Info: Elapsed time: 00:00:29
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