data_scanc.v

来自「Verilog 经典实例」· Verilog 代码 · 共 61 行

module data_scanC
	( sys_clk,
	k_data,
	k_clock,
	reset,
	data,
	PA,
	ZHJS
	);
	input sys_clk;
	input k_data;
	input k_clock;
	input reset;
	output [7:0] data;
	inout  [7:0] PA;
	inout  ZHJS;
	
	reg  [11:0]  tmp = 11'b000_0000_0000;
	reg  now_kbclk, pre_kbclk;   
	reg  ZHJS;
	reg  started = 0;
	reg  [3:0] counter = 0;
	wire  enable;
	
	always @(posedge sys_clk or negedge reset)
	begin
	   if(!reset) begin
	     ZHJS <= 0;
	     counter = 0;
	   end
	   else begin
	     pre_kbclk <= now_kbclk;
	     now_kbclk <= k_clock;
	     if(pre_kbclk > now_kbclk) begin
			tmp[counter] <= k_data;
			if(counter == 4'd10) begin
			  ZHJS <= 1'b0;
			end
			else begin
			  ZHJS <= 1'b1;
			end
			if(counter == 4'd11) begin
			  counter <= 4'd1;
			end
			else begin
			  counter <= counter + 1;
			end
		 end // end of if(pre_kbclk > now_kbclk)
	     if(counter > 4'd1 && counter <4'd10 ) begin
	        started <= 1'b1;
	     end
	     else begin
	        started <= 1'b0;
	     end
	   end 
	end
	
	assign enable = started;
	assign PA = enable ? 8'b0000_0000 : tmp[8:1];
	assign data = PA;
	endmodule