📄 counter.vhd
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LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY Counter IS
PORT ( Clock: in Std_logic;
Reset: in Std_logic;
Hold: in Std_logic;
CountNum: buffer Integer range 0 to 49 );
END Counter ;
ARCHITECTURE behavior OF Counter IS
BEGIN
PROCESS(Reset,Clock)
BEGIN
IF reset ='1' then
CountNum<=0;
elsif rising_edge(clock) then
if Hold='1' then
CountNum<=CountNum;
else
if CountNum=49 then
CountNum<=0;
else
CountNum<=CountNum+1;
end if;
end if;
END IF;
END PROCESS;
END ;
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