dds.fit.summary

来自「基于DDS原理的正弦信号发生器。用VERILOG语言实现」· SUMMARY 代码 · 共 17 行

Fitter Status : Successful - Mon Jul 28 11:06:11 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : DDS
Top-level Entity Name : DDDS
Family : Cyclone II
Device : EP2C35U484C8
Timing Models : Final
Total logic elements : 31 / 33,216 ( < 1 % )
    Total combinational functions : 31 / 33,216 ( < 1 % )
    Dedicated logic registers : 21 / 33,216 ( < 1 % )
Total registers : 21
Total pins : 35 / 322 ( 11 % )
Total virtual pins : 0
Total memory bits : 10,240 / 483,840 ( 2 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 1 / 4 ( 25 % )