dds.hier_info

基于DDS原理的正弦信号发生器。用VERILOG语言实现

|DDDS
sync <= DDS:inst.sync
clk => altpll0:inst1.inclk0
reset_n => DDS:inst.reset_n
freqword[0] => DDS:inst.freqword[0]
freqword[1] => DDS:inst.freqword[1]
freqword[2] => DDS:inst.freqword[2]
freqword[3] => DDS:inst.freqword[3]
freqword[4] => DDS:inst.freqword[4]
freqword[5] => DDS:inst.freqword[5]
freqword[6] => DDS:inst.freqword[6]
freqword[7] => DDS:inst.freqword[7]
freqword[8] => DDS:inst.freqword[8]
freqword[9] => DDS:inst.freqword[9]
freqword[10] => DDS:inst.freqword[10]
freqword[11] => DDS:inst.freqword[11]
freqword[12] => DDS:inst.freqword[12]
freqword[13] => DDS:inst.freqword[13]
freqword[14] => DDS:inst.freqword[14]
freqword[15] => DDS:inst.freqword[15]
freqword[16] => DDS:inst.freqword[16]
freqword[17] => DDS:inst.freqword[17]
freqword[18] => DDS:inst.freqword[18]
freqword[19] => DDS:inst.freqword[19]
blank <= DDS:inst.blank
clkout <= DDS:inst.clkout
sinout[0] <= DDS:inst.sinout[0]
sinout[1] <= DDS:inst.sinout[1]
sinout[2] <= DDS:inst.sinout[2]
sinout[3] <= DDS:inst.sinout[3]
sinout[4] <= DDS:inst.sinout[4]
sinout[5] <= DDS:inst.sinout[5]
sinout[6] <= DDS:inst.sinout[6]
sinout[7] <= DDS:inst.sinout[7]
sinout[8] <= DDS:inst.sinout[8]
sinout[9] <= DDS:inst.sinout[9]


|DDDS|DDS:inst
clk => sinout[9]~reg0.CLK
clk => sinout[8]~reg0.CLK
clk => sinout[7]~reg0.CLK
clk => sinout[6]~reg0.CLK
clk => sinout[5]~reg0.CLK
clk => sinout[4]~reg0.CLK
clk => sinout[3]~reg0.CLK
clk => sinout[2]~reg0.CLK
clk => sinout[1]~reg0.CLK
clk => sinout[0]~reg0.CLK
clk => add[19].CLK
clk => add[18].CLK
clk => add[17].CLK
clk => add[16].CLK
clk => add[15].CLK
clk => add[14].CLK
clk => add[13].CLK
clk => add[12].CLK
clk => add[11].CLK
clk => add[10].CLK
clk => add[9].CLK
clk => add[8].CLK
clk => add[7].CLK
clk => add[6].CLK
clk => add[5].CLK
clk => add[4].CLK
clk => add[3].CLK
clk => add[2].CLK
clk => add[1].CLK
clk => add[0].CLK
clk => clkout.DATAIN
reset_n => sinout[0]~reg0.ACLR
reset_n => sinout[1]~reg0.ACLR
reset_n => sinout[2]~reg0.ACLR
reset_n => sinout[3]~reg0.ACLR
reset_n => sinout[4]~reg0.ACLR
reset_n => sinout[5]~reg0.ACLR
reset_n => sinout[6]~reg0.ACLR
reset_n => sinout[7]~reg0.ACLR
reset_n => sinout[8]~reg0.ACLR
reset_n => sinout[9]~reg0.ACLR
reset_n => add~19.OUTPUTSELECT
reset_n => add~18.OUTPUTSELECT
reset_n => add~17.OUTPUTSELECT
reset_n => add~16.OUTPUTSELECT
reset_n => add~15.OUTPUTSELECT
reset_n => add~14.OUTPUTSELECT
reset_n => add~13.OUTPUTSELECT
reset_n => add~12.OUTPUTSELECT
reset_n => add~11.OUTPUTSELECT
reset_n => add~10.OUTPUTSELECT
reset_n => add~9.OUTPUTSELECT
reset_n => add~8.OUTPUTSELECT
reset_n => add~7.OUTPUTSELECT
reset_n => add~6.OUTPUTSELECT
reset_n => add~5.OUTPUTSELECT
reset_n => add~4.OUTPUTSELECT
reset_n => add~3.OUTPUTSELECT
reset_n => add~2.OUTPUTSELECT
reset_n => add~1.OUTPUTSELECT
reset_n => add~0.OUTPUTSELECT
freqword[0] => Add0.IN20
freqword[1] => Add0.IN19
freqword[2] => Add0.IN18
freqword[3] => Add0.IN17
freqword[4] => Add0.IN16
freqword[5] => Add0.IN15
freqword[6] => Add0.IN14
freqword[7] => Add0.IN13
freqword[8] => Add0.IN12
freqword[9] => Add0.IN11
freqword[10] => Add0.IN10
freqword[11] => Add0.IN9
freqword[12] => Add0.IN8
freqword[13] => Add0.IN7
freqword[14] => Add0.IN6
freqword[15] => Add0.IN5
freqword[16] => Add0.IN4
freqword[17] => Add0.IN3
freqword[18] => Add0.IN2
freqword[19] => Add0.IN1
sync <= <GND>
blank <= <VCC>
sinout[0] <= sinout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[1] <= sinout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[2] <= sinout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[3] <= sinout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[4] <= sinout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[5] <= sinout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[6] <= sinout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[7] <= sinout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[8] <= sinout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sinout[9] <= sinout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
clkout <= clk.DB_MAX_OUTPUT_PORT_TYPE


|DDDS|DDS:inst|rom0:rom0_instant
ad[0] => Ram0.RADDR
ad[1] => Ram0.RADDR1
ad[2] => Ram0.RADDR2
ad[3] => Ram0.RADDR3
ad[4] => Ram0.RADDR4
ad[5] => Ram0.RADDR5
ad[6] => Ram0.RADDR6
ad[7] => Ram0.RADDR7
ad[8] => Ram0.RADDR8
ad[9] => Ram0.RADDR9
q[0] <= Ram0.DATAOUT
q[1] <= Ram0.DATAOUT1
q[2] <= Ram0.DATAOUT2
q[3] <= Ram0.DATAOUT3
q[4] <= Ram0.DATAOUT4
q[5] <= Ram0.DATAOUT5
q[6] <= Ram0.DATAOUT6
q[7] <= Ram0.DATAOUT7
q[8] <= Ram0.DATAOUT8
q[9] <= Ram0.DATAOUT9


|DDDS|altpll0:inst1
inclk0 => sub_wire3[0].IN1
c0 <= altpll:altpll_component.clk


|DDDS|altpll0:inst1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <= <GND>
clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= <GND>
clk[2] <= <GND>
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>