dds.map.qmsg

基于DDS原理的正弦信号发生器。用VERILOG语言实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 28 11:05:49 2008 " "Info: Processing started: Mon Jul 28 11:05:49 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDS.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file DDS.v" { { "Info" "ISGN_ENTITY_NAME" "1 DDS " "Info: Found entity 1: DDS" {  } { { "DDS.v" "" { Text "E:/DDS/DDS.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 rom0 " "Info: Found entity 2: rom0" {  } { { "DDS.v" "" { Text "E:/DDS/DDS.v" 40 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDDS.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DDDS.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DDDS " "Info: Found entity 1: DDDS" {  } { { "DDDS.bdf" "" { Schematic "E:/DDS/DDDS.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DDDS " "Info: Elaborating entity \"DDDS\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DDS DDS:inst " "Info: Elaborating entity \"DDS\" for hierarchy \"DDS:inst\"" {  } { { "DDDS.bdf" "inst" { Schematic "E:/DDS/DDDS.bdf" { { 8 400 584 136 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 DDS:inst\|rom0:rom0_instant " "Info: Elaborating entity \"rom0\" for hierarchy \"DDS:inst\|rom0:rom0_instant\"" {  } { { "DDS.v" "rom0_instant" { Text "E:/DDS/DDS.v" 36 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "altpll0.v 1 1 " "Warning: Using design file altpll0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 altpll0 " "Info: Found entity 1: altpll0" {  } { { "altpll0.v" "" { Text "E:/DDS/altpll0.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll0 altpll0:inst1 " "Info: Elaborating entity \"altpll0\" for hierarchy \"altpll0:inst1\"" {  } { { "DDDS.bdf" "inst1" { Schematic "E:/DDS/DDDS.bdf" { { -224 72 312 -64 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/72/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 476 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll altpll0:inst1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"altpll0:inst1\|altpll:altpll_component\"" {  } { { "altpll0.v" "altpll_component" { Text "E:/DDS/altpll0.v" 88 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "altpll0:inst1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"altpll0:inst1\|altpll:altpll_component\"" {  } { { "altpll0.v" "" { Text "E:/DDS/altpll0.v" 88 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "DDS:inst\|rom0:rom0_instant\|Ram0~19 " "Info: Inferred altsyncram megafunction from the following design logic: \"DDS:inst\|rom0:rom0_instant\|Ram0~19\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE ROM " "Info: Parameter OPERATION_MODE set to ROM" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 10 " "Info: Parameter WIDTH_A set to 10" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 10 " "Info: Parameter WIDTHAD_A set to 10" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 1024 " "Info: Parameter NUMWORDS_A set to 1024" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter OUTDATA_REG_A set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_A NONE " "Info: Parameter OUTDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Info: Parameter RAM_BLOCK_TYPE set to AUTO" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/rom0_rom0_3af052.hdl.mif " "Info: Parameter INIT_FILE set to db/rom0_rom0_3af052.hdl.mif" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0}  } { { "DDS.v" "Ram0~19" { Text "E:/DDS/DDS.v" 46 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "DDS:inst\|rom0:rom0_instant\|altsyncram:Ram0_rtl_0 " "Info: Elaborated megafunction instantiation \"DDS:inst\|rom0:rom0_instant\|altsyncram:Ram0_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4m71.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4m71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4m71 " "Info: Found entity 1: altsyncram_4m71" {  } { { "db/altsyncram_4m71.tdf" "" { Text "E:/DDS/db/altsyncram_4m71.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "sync GND " "Warning (13410): Pin \"sync\" stuck at GND" {  } { { "DDDS.bdf" "" { Schematic "E:/DDS/DDDS.bdf" { { 32 616 792 48 "sync" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "blank VCC " "Warning (13410): Pin \"blank\" stuck at VCC" {  } { { "DDDS.bdf" "" { Schematic "E:/DDS/DDDS.bdf" { { 48 616 792 64 "blank" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "77 " "Info: Implemented 77 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Info: Implemented 22 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "31 " "Info: Implemented 31 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "10 " "Info: Implemented 10 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "146 " "Info: Allocated 146 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 28 11:05:55 2008 " "Info: Processing ended: Mon Jul 28 11:05:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}