dds.tan.summary

基于DDS原理的正弦信号发生器。用VERILOG语言实现

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 9.626 ns
From           : freqword[4]
To             : DDS:inst|add[19]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.550 ns
From           : DDS:inst|rom0:rom0_instant|altsyncram:Ram0_rtl_0|altsyncram_4m71:auto_generated|ram_block1a0~porta_address_reg9
To             : sinout[0]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -6.875 ns
From           : freqword[0]
To             : DDS:inst|add[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'altpll0:inst1|altpll:altpll_component|_clk0'
Slack          : 2.877 ns
Required Time  : 150.02 MHz ( period = 6.666 ns )
Actual Time    : 263.92 MHz ( period = 3.789 ns )
From           : DDS:inst|add[0]
To             : DDS:inst|add[19]
From Clock     : altpll0:inst1|altpll:altpll_component|_clk0
To Clock       : altpll0:inst1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'altpll0:inst1|altpll:altpll_component|_clk0'
Slack          : 1.148 ns
Required Time  : 150.02 MHz ( period = 6.666 ns )
Actual Time    : N/A
From           : DDS:inst|add[1]
To             : DDS:inst|add[1]
From Clock     : altpll0:inst1|altpll:altpll_component|_clk0
To Clock       : altpll0:inst1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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