pll.bsf

基于DDS原理的正弦信号发生器。用VERILOG语言实现

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 64 64 304 224)
	(text "PLL" (rect 109 0 136 16)(font "Arial" (font_size 10)))
	(text "inst" (rect 8 144 25 156)(font "Arial" ))
	(port
		(pt 0 64)
		(input)
		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
		(text "inclk0" (rect 4 51 35 65)(font "Arial" (font_size 8)))
		(line (pt 0 64)(pt 40 64)(line_width 1))
	)
	(port
		(pt 240 64)
		(output)
		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
		(text "c0" (rect 225 51 239 65)(font "Arial" (font_size 8)))
		(line (pt 240 64)(pt 208 64)(line_width 1))
	)
	(drawing
		(text "Cyclone II" (rect 183 145 234 157)(font "Arial" ))
		(text "inclk0 frequency: 50.000 MHz" (rect 50 59 197 71)(font "Arial" ))
		(text "Operation Mode: Normal" (rect 50 73 169 85)(font "Arial" ))
		(text "Clk " (rect 51 96 71 108)(font "Arial" ))
		(text "Ratio" (rect 73 96 98 108)(font "Arial" ))
		(text "Ph (dg)" (rect 100 96 135 108)(font "Arial" ))
		(text "DC (%)" (rect 135 96 171 108)(font "Arial" ))
		(text "c0" (rect 54 111 65 123)(font "Arial" ))
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)
(symbol
	(rect 64 64 304 224)
	(text "PLL" (rect 109 0 136 16)(font "Arial" (font_size 10)))
	(text "inst" (rect 8 144 25 156)(font "Arial" ))
	(port
		(pt 0 64)
		(input)
		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
		(text "inclk0" (rect 4 51 35 65)(font "Arial" (font_size 8)))
		(line (pt 0 64)(pt 40 64)(line_width 1))
	)
	(port
		(pt 240 64)
		(output)
		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
		(text "c0" (rect 225 51 239 65)(font "Arial" (font_size 8)))
		(line (pt 240 64)(pt 208 64)(line_width 1))
	)
	(drawing
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		(text "inclk0 frequency: 50.000 MHz" (rect 50 59 197 71)(font "Arial" ))
		(text "Operation Mode: Normal" (rect 50 73 169 85)(font "Arial" ))
		(text "Clk " (rect 51 96 71 108)(font "Arial" ))
		(text "Ratio" (rect 73 96 98 108)(font "Arial" ))
		(text "Ph (dg)" (rect 100 96 135 108)(font "Arial" ))
		(text "DC (%)" (rect 135 96 171 108)(font "Arial" ))
		(text "c0" (rect 54 111 65 123)(font "Arial" ))
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	)
)