dds.map.summary

基于DDS原理的正弦信号发生器。用VERILOG语言实现

Analysis & Synthesis Status : Successful - Mon Jul 28 11:05:55 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : DDS
Top-level Entity Name : DDDS
Family : Cyclone II
Total logic elements : 30
    Total combinational functions : 30
    Dedicated logic registers : 21
Total registers : 21
Total pins : 35
Total virtual pins : 0
Total memory bits : 10,240
Embedded Multiplier 9-bit elements : 0
Total PLLs : 1